Hi, it is my understanding that the OpAmp or comparator offset is caused by the mismatch of the transistors (mainly the input differential pair?). so how to exactly measure the input-referred offset voltage in Cadence virtuoso schematic environment? Do I have to add mismatch in the transistor models? Thanks.

A "dcmatch" analysis would also be a very good first approach. In the case of the comparator its input should be balanced when running the analysis, since it is the condition at which it will change its state and therefore when offset is meaningful.

Regards
Tosei