Are you concerned about noise folding in later stages?  Obviously, at really high frequency, you are talking about the direct transmission through all of your parasitic caps.  Since the active elements have all lost their gains by then, you have to resort to capacitor tricks.  What architecture are you using?

Hi Tosei,

In addition to choosing a better opamp architecture, there is also the possibility of reducing HF noise on the supply. I think you are not really talking about noise but interferers at HF.

Have you considered using some EMI-reduction schemes on the supply? Depending on the amount of current drawn, you may be able to get away with some small R and large C to filter out the HF noise from supply. An LDO may also help significantly in curbing HF noise.

Depending on the exact requirements on your system, this may be less painful than making an opamp that can reject the HF noise.

As for the common mode (in this case it is the signal if you have SE amps), you need to give some thought to schemes which are inherently filtering. I gather that you are buffering some DC levels. In that case, filtering the input to the amp is a highly effective way to remove HF noise.

Regards,

Vivek

This seems an interesting topic.
It is not clear for me what is the mechanisms that causes folding of HF into DC.  Is this being used in an ADC?
Or is your application a demodulator?

Cheers,
Humberto

HdrChopper wrote on Nov 17^th, 2008, 2:31am:


Hi Tosei,

In this case, I would advise even more strongly that you consider input filtering to eliminate HF interference. Supply filering should also help a lot. Usually, LDOs will provide atleast 1 level of supply rejection even at HF, depending on realization, which may not be sufficient by itself but could be supplemented with other things.

You will need to spend more area and maybe power if you want to get rid of HF noise. For filtering the input, you don't have to worry about I*R drop in the R but you also don't want more noise. So, you will be forced to use a large C and a moderate R. For filtering the supply, you have I*R drop to consider, and so you will have to use a small R and a large C. These are passive design tricks which you call "brute-force".

There are several active design tricks but I doubt if any will work at really high frequencies, because any active circuitry which has to filter out or suppress the HF noise will need large current to have high enough BW, and will itself be subject to the effect you are trying to suppress (demodulation).

Layout is critical for all approaches.

For the opamp, I would use a non-Miller structure for better PSRR, especially if there is noise at both VDD and GND. The Ahuja structure is your best bet (B. K. Ahuja, JSSC, Dec. '83 I think).

Regards,

Vivek

Hi Tosei,


1/ Yes: The miller compensation is not famous for its PSRR, try cascode compensation. Therefore you would need cascode below your pmos input pair to implement that.
PSRR performance increases according to the square root of the gbandwidth product, it is worth trying I guess..
I ve implemented such kind of cascode compensation you can ask me for further detail if required.

( I assume you already know this: 2/ for Pmos input pair,  using more cascode layer to bias your input pair this will improve PSRR as well )

3/ You can try to use an automatic offset correction circuit where the output of your amplifier goes into very low bandwidth low pass filter (where the resistance is the Rds of transitor bias in saturation+ couple of pico farad caps) that basically extract the DC component then difference in voltage with respect to a desire common mode voltage is translated into current into the differential pair...

Have a nice night.

Tareeq.