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IJnte

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Pionter functionality with Verilog-AMS
Nov 20^th, 2008, 1:18am

Dear all,

I'm currently working on a self-checking automatic testbench in Verilog-AMS for IP modules. I have Ken's book (designer's guide to Verilog-AMS), but i still have a few questions:

Is it possible to create a pointer to an input or output of a model, in combination with a task or function ? For example if i have this code(not checked at all!!):
Code:

module testblock(input1, input2, output1, output2);
input input1, input2;
ouput output1, output2;
electrical input1, input2;
logic output1, output2;
.....
....
(some more code)
begin
   task_check_input(&input1);
end

task_check_input;
input choice_input;
real *choice_input;
real voltage;
begin
    voltage <= V(choice_input,gnd);
    ......
end
endtask

Ofcource it is possible to constantly monitor a analog value within the analog statements in verilog-ams. I'm just wondering if it is possible to use pointers within Verilog-AMS. I can imagine that it is not posible although..

Second question i have, is about the verification of a behaviour model v.s. a transistormodel. Does anybody knows how to verify the two models with 1 (verilog-ams) testbench at the same time. At this point i am simulation the behaviour model and the transistor model seperate, and then compare the output of both models but i would like to do this in 1 check. Does someone has a tip

Kind regards,

IJnte

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Peruzzi

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Re: Pionter functionality with Verilog-AMS
Reply #1 - Nov 20^th, 2008, 9:21am

IJnte,

What are you actually trying to do? Maybe there's another way to accomplish the same thing. I've never seen pointers like that in Verilog-AMS. In VHDL-AMS there's something called an enumerated type but I couldn't find something similar in Ken's book.

I wonder if you can accomplish what you're trying to do by passing an array of string variables to your task or function. At present I don't have access to a simulator so I can't play around with it.

If you solve it on your own, do me a favor and post your solution.

Best regards,

Bob P.

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IJnte

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Re: Pionter functionality with Verilog-AMS
Reply #2 - Nov 20^th, 2008, 11:50am

Dear Bob P. ,

Thank you for you reply!

I'm currently working on the concept of self-checking test benches with Verilog-AMS. I already have made one with small tasks that each perform a check on parameters.
However, i would like to make this tasks as universal as possible. I;ve had some inspiration from some presentation that i have from Ken (my collegues followed some courses) about small tasks that perform checks within a testbench.
When i have an device with lets say 100 input, i don't want to make 100 seperate analog statements (volt_level_x <= V(input, gnd)).. I would rather make a task or function on which you can give a "pointer" to an input.
At this moment i just use some more code within the analog statement, but i am also looking into the future

At this moment we are really pushing to change our way-of-working towards a rigorous top-down methode. This is ofcourse a very though transition, but we are gaining experiance. One of the tools for this top-down WOW is the use of self-checking testbenches.
The story about this way-of-working in Ken's book is very clear en recognizable.

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Peruzzi

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Re: Pionter functionality with Verilog-AMS
Reply #3 - Nov 20^th, 2008, 6:31pm

All worthy goals. �I'm a true believer when it comes to top-down design, and bottom-up verification.

Regarding your second question -- verifying models versus schematics. �Please be aware that depending on how you will put the model to use, you may not want exact match to the transistors. � Three examples are a PLL, LDO, Switch-mode DCDC converter. �For mixed-signal SOC verification, you probably want these to have coarse behavioral models in 99% of your test cases.

But to directly address your question of how to verify model versus schematic, there are two approaches:

My preferred test bench instantiates the DUT symbol and a Driver/Monitor symbol. �I make a Verilog-AMS model to drive all the DUT inputs and monitor and test all the outputs. �I use the hierarchy editor to set the DUT view to schematic, run the simulation and save the output plots. �For subsequent runs I set the DUT view to verilogams. �Then I repeatedly rerun the model simulation as needed while revising the model.

The other test bench option instantiates two DUTs, one represented by the model view and the other by the schematic view. �Also there's a Driver/Monitor. �It can be very similar to that of the other method but be sure not to do something silly like connect the same current source to both DUTs Wink

I hope this is clear. �Reply if not.

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IJnte

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Re: Pionter functionality with Verilog-AMS
Reply #4 - Nov 21^st, 2008, 1:54am

Hi Bob P.,

You're preferred methode (the first one) is the way how we do it now! We make a testbench for a model. This testbench is made with Verilog-AMS and has automatic check features integrated into this design. After the creation of a testbench, we make a schematic with the DUT and the V-AMS testbench. In the hierarchy editor of Cadence we select the schematic and then test the functionallity of the DUT. After this we change the DUT to the behaviour model and then rerun the test again. Although this is a good and solid solution, it still costs valuable time to check the output of both tests (besided the Pass/Fail checks within the V-AMS testbench). I thought there was a better solution for this, to combine the two in 1 overall test.

The second option you mention is a methode that is preferable, because it is able to test the model and the schematic in 1 test. In this way you can always verify if the schematic and the model are equal en consistant. The difficulty though, is that you need to make two seperate designs of the same schematic for the implementation in Cadence... AFAIK you cannot select different views (schematic of behaviour) if you have two identical symbols in you're schematic.

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Frank Wiedmann Community Fellow Offline Posts: 677 Munich, Germany	Re: Pionter functionality with Verilog-AMS Reply #5 - Nov 21^st, 2008, 6:24am You should be able to select the view for each instance either in the Instance Table or the Tree View of the Hierarchy Editor, which you can select from its View menu.
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Peruzzi

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Re: Pionter functionality with Verilog-AMS
Reply #6 - Nov 21^st, 2008, 1:18pm

IJnte,

Regarding:

IJnte wrote on Nov 21^st, 2008, 1:54am:

Although this is a good and solid solution, it still costs valuable time to check the output of both tests (besided the Pass/Fail checks within the V-AMS testbench). I thought there was a better solution for this, to combine the two in 1 overall test.

I wonder..., �Isn't the extra time it takes to run the transistor-level schematic much greater than the time it takes to eyeball the transient plots? �The output checking can be streamlined if you save the script to plot both the reference transistor-level transient output along with the latest model transient output. �Keep in mind that the point of this exercise is to validate the model, and only needs to be done when the model is revised. �Investing too much time in automating the validation may not be valuable.

I also have used the tree-view to select the model view for one instance and schematic for the other. �This comes in handy if you're debugging a stubborn timing problem and must set a few logic gate instances to schematics, and leave all the others as digital models.

Hope this helps.

Bob P.

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IJnte

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Re: Pionter functionality with Verilog-AMS
Reply #7 - Nov 25^th, 2008, 11:35pm

Peruzzi wrote on Nov 21^st, 2008, 1:18pm:

IJnte,

Regarding:

IJnte wrote on Nov 21^st, 2008, 1:54am:

Although this is a good and solid solution, it still costs valuable time to check the output of both tests (besided the Pass/Fail checks within the V-AMS testbench). I thought there was a better solution for this, to combine the two in 1 overall test.

I wonder..., �Isn't the extra time it takes to run the transistor-level schematic much greater than the time it takes to eyeball the transient plots? �The output checking can be streamlined if you save the script to plot both the reference transistor-level transient output along with the latest model transient output. �Keep in mind that the point of this exercise is to validate the model, and only needs to be done when the model is revised. �Investing too much time in automating the validation may not be valuable.

I also have used the tree-view to select the model view for one instance and schematic for the other. �This comes in handy if you're debugging a stubborn timing problem and must set a few logic gate instances to schematics, and leave all the others as digital models.

Hope this helps.

Bob P.

Yes, I agree with you about the investigation in more automation. All automated processing should not be te goal, but automation in itself is a great tool.
Thank you for you're answer!

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