Hi all! In the design of an analog pulse receiver, I  have come across with the need of generating a pair of control signals as shown below in "Figure 1". The control signals "A" and "B" must meet the following constraints (please see Figure 1):

C1. The rising edge of signal "A" should be synchronized with the falling edge of signal "B". The relative skew between these two edges should be as close as possible to zero for all process and temperature corners.
C2. The pulse width of (the low portion of) signal "A" should be 1ns nominally, and as stable as possible against all process and temperature corners.
C3. Both control signals should be generated from a 100MHz clock. The relative phase of the signals with respect to this clock is not important, as long as it is deterministic.
C4. Last but not least, signal "A" should drive an equivalent load CA=300fF, while signal "B" should drive CB=1pF.

I first tried a very obvious approach (please see Figure 2 below) that uses a couple of inverters to generate the 1ns delay measure and then a RS latch to obtain the desired wave shape for signal "A"; signal "B" being just the delayed version of the clock (and inverted). Then I added inverter chains to buffer the signals in order to drive the large load capacitances CA and CB.

The main problem with the above solution is that I am largely unable to meet constraints C1 and C2. Using this approach the effective width of pulse "A" is determined by the inverters in the "delay generator", while the relative phase between A and B depends largely on the delays of their respective buffer chains. As a result, they both vary *a lot* across process and temperature corners, as sketched in Figure 3.

So now my idea is to solve these problems is as follows (see Figure 4 below):

1.-Make use of a trimmable delay generator for generating the 1ns pulse width for signal "A", so I could adjust digitally this parameter and meet constraint C2.
2.-Synchronize the rising edge of "A" with the falling edge of "B" using a delay locked loop (DLL), so I could guarantee constraint C1 against all process variations.

I think I can manage to figure out about the trimmable delay generator. My problem is that I have never designed before a DLL; I would like to keep it as simple as possible, but I am unsure of the following:

-Is the DLL approach in Figure 4 likely to work? Is this the usual way to generate synchronized control signals in analog chips?
-If the DLL approach is suitable, what type of phase detector would be advisable to use, considering the waveform shapes and the 1ns detail in signal "A"? How can I determine the most suitable detector type?  
-What type of low pass filter should I use? How can I infer the required characteristics?
-What type of delay elements should I use for the variable delay line?
-Again, last but not least, what would be a realistic estimate for the design time of the DLL? I am using a 0.35 CMOS process.

Please, any ideas/opinions/references/clues are welcome. Thanks in advance for any help, and sorry for the long post!  

Cheers,

Jorge.

Figure 2 - First (naive) solution

Figure 4 - Proposed solution making use of a digitally-trimmable delay generator and a DLL.