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ESD help--how to protect digital register from ESD (Read 6783 times)
andyjackcao
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ESD help--how to protect digital register from ESD
Dec 09th, 2008, 6:31am
 
Hi guys

there is big trouble about my TP system esd protection;

although my IC has pass the 8KV about nake test,

yet the system esd level is still low;

when I test the the state of ADC, I found the state of register had been

disturbed ;

so I want to know the way of protecting IC from ESD,when I  begen

a IC'S esd design

THS very much

regards

andyjackcao
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my mail is andyjackcao@sina.com;
I am focus on analog IC,that is wonderful!
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Re: ESD help--how to protect digital register from ESD
Reply #1 - Dec 10th, 2008, 11:42am
 
Hi Andy,
Can you explain the difference in your testing?  How did you test your IC to 8kV and how are you testing your system?  A brief description of the test setup for both would be invaluable.
Thanks,
 Stephen
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andyjackcao
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Re: ESD help--how to protect digital register from ESD
Reply #2 - Dec 11th, 2008, 5:59am
 
SRF Tech wrote on Dec 10th, 2008, 11:42am:
Hi Andy,
Can you explain the difference in your testing?  How did you test your IC to 8kV and how are you testing your system?  A brief description of the test setup for both would be invaluable.
Thanks,
 Stephen


thanks for you repley
A,
the IC test is done by anthoer ESD test company, they test my IC according to the MIL standard;In the test pins,we select several  important pins including VCC_pin  GND_pin IO_pin ANALOG_pin;
ANALOG_pin vs GND has passed 8kv

B,
System test is done by ourselves;
A ESD pulse generated by a ESD equipment has been put on the TP liquid crystal screen,yet,my system only pass 5k;then the system could rework after power reset

since the ESD protection of 4 pins connected to liquid crystal screen are 4 analog pins  passed 8k,then I detect some test signal to find some strange phenomenon,that is the ADC control signal is abnormal;

in fact ,the control signal is determined by digital register, so I suspect
there is something wrong with the digital part

regards
andyjackcao
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my mail is andyjackcao@sina.com;
I am focus on analog IC,that is wonderful!
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Re: ESD help--how to protect digital register from ESD
Reply #3 - Dec 12th, 2008, 7:08pm
 
Hi Andy,
 I still do not understand your test procedures enough to offer good advice.  Can you answer the following questions:

1. When you say an "ESD Test house" tested the IC against the MIL standard to 8kV, do you know what equipment they used and how they performed the test?

2. For your system level test you are doing yourself, what is your "ESD Equipment"?

3. Can you describe the system a little, you mention your ananlog IC, and a "digital" part.  What is the digital part and how is it related to your analog IC, what is their relation to the rest of the system.  (This question may be far too broad for this forum as I would almost need a schematic with power/GND routing descriptions.)

I will say this, the ESD testing of an IC has very little correlation to system level testing.  For an example, please read my comment in this post: http://www.designers-guide.org/Forum/YaBB.pl?num=1226827296

So even if your Part is tested to the MIL standard, it will have no bearing on how that part or a system using that part will pass the MIL standard.  The primary reason is that when you test the IC, you strictly control the return current paths, but in a system, the return current paths are dictated by the system design and may not be the same as the IC test, therefore the test results may not be the same.

Essentially, System tests do not correlate well with standalone IC tests and vice versa.  System test have also been notorious in that reliable and repeatable system models have yet to be developed in the industry.

Its particularly bad when people try testing with "ESD zap guns".  They are cheap and available but they do not make good ESD testers, either for an IC or a system.  They only thing they are really useful for is testing conductance and discharged requirements for standards such as MIL, CE mark, UL, etc.

Hope this helps.
-Stephen
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flyfeng
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Re: ESD help--how to protect digital register from ESD
Reply #4 - Dec 13th, 2008, 3:49am
 
Hello,stephen,
let me answer your questions.
1. This test means componet-level test for our ICs.
2.ESD equipment is "ESD gun" for our system-level.
3.The system that I describe here may be some complex.I'll try to explain it clearly.
 This is the system using an IC for controlling a touch panel above LCD in mobile phones.When I do the system level esd test, I zap the
edge of the TP(touch panel),and 4 pins of the IC are connected to the TP through FPC.So when ESD zap the edge of the TP,the 4 pins are influenced seriously and these 4 pins we thought are analog pins.
 And these 4 pins are protected by two diode between themslves and VDD ,between themselvs and GND. So when the ESD event occurs, VCC and GND are influenced,and the power of  the internal digital part of the IC connected with the VCC BUS and GND BUS are also changed in the moment that ESD occurs. So the data of the digital register are changed.
 So, we cannot send correct data to MCU and MCU cannot have feedback. The status we thought is in lock ,unless the power is off;when the power is on, the system is OK.
 Especially,the voltage of the 4 pins connected with TP is controlled by 4 digital signal,and are changed after ESD system-level test.But we could not understand why the voltage would be those volumes.
We try to analyze the reason, the above was what we thought. I don't know whether it is right.

I hope you could understan what I say.
thanks for your help.
Best wishes.
                   Heaven
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Re: ESD help--how to protect digital register from ESD
Reply #5 - Dec 15th, 2008, 8:30am
 
Hi guys,
So there are several issues to discuss and sort out.

First, your analog part passed an "ESD Test" to 8kV.  This test was likely performed on test equipment designed for ESD stressing.  Also the part was stressed, most likely, in an un-powered non-functional state, and then tested for functionality post-stress.

This test in no way correlates with what you are doing with the ESD gun.  Big difference as I already mentioned.  

Your part survived an ESD stress, but it was not tested to survive an ESD stress while it was operating.  

Your system level test is however.  So I want you to stop comparing the two test, they are not related, at all.  Also, your testing with an ESD Gun, which as I have stated in previous posts, does not look at all like the ESD waveform developed by a Component level ESD tester.

Your real question is what is happening to our system during the Gun Zap.  Your proposed problem is possibly correct, that your coupling massive charge into the power and GND busses that are affecting the digital section of the IC.  That is not a bad theory, and remember your component level testing did not test for how your part would react to the pulses during operation.

In summary, you can not correlate your component testing with your system test.  So your only challenge is trying to figure out whats causing the system failure.  Your theory seems sound to me, and without in-depth knowledge of your system I can not debunk it or propose a better theory, but I have seen ESD gun zaps to pins of a part cause it to reset or lock up, that is quite normal.

If your theory is correct, there are several potential solutions but again, its requires more in-depth knowledge of the system for me to responsibly propose anything.

Also, consider the standard you are testing against, some standards allow for a part to survive a gun zap and pass after a soft error (which is fixed by a reset) and others require the system to survive a zap without interruption to operation.  I don't know what your goal is or needs to be, but you may be fine, just check your standard.  (I only say this because on many occasions, customers of mine have been meeting their goals but were unaware of it because they had implied a level of performance outside their standard).

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