**prince_123 wrote on Jan 4**^{th}, 2009, 10:04pm:Dear All

DNL - (Differential Non linearity) is characteristic of any data converter.

I would like to know how to predict DNL graph in pipelined ADC when you have

1. Only gain error in OTA, all other components are ideal.

2. Offset error in flash comparators and all other components are ideal.

3. How is the choice of Vref (Reference voltage) affects the final DNL graph.

If some one can explain it in an intuitive way, it will be of great help to understand pipeline ADC better.

Regards prince

Hi,

That is not at all any easy question to answer, especially posting onto a forum. Let me try to answer one part (effect of finite opamp gain), and you can extend the same to other nonidealities:

Assume the simplest pipeline ADC (1.5b stage) with a gain of 2. This has a piecewise linear characteristic with a slope of exactly 2 V/V and discontinuity at the thresholds of the 2 comparators, at +Vr/4 and -Vr/4, if we denote the full signal range as spanning from -Vr to +Vr, where Vr is the reference voltage.

Finite gain in the opamp will mean that the slope will be slightly less than 2 V/V, more precisely, it will be approx. 2 (1-Adc). Ideally, the discontinuity at each comparator threshold would have had a step height of exactly Vr, but now this shrinks by approx. 2*Vr/Adc. This is the DNL of your pipeline stage due to finite opamp gain.

Anything which changes the slope of the gain curve will cause DNL in the same manner, because your digital postprocessing of the bits from each stage assumes that the gain is 2 V/V.

Comparator offsets in the 1.5 b/stage scheme will only cause the thresholds to move around, but as long as the movement is smaller than +/-Vr/4, this should be OK as the stage output does not exceed the limits (-Vr,+Vr).

Regards,

Vivek

P.S. I might have a factor of 2 missing somwhere in my expressions. Just write out the expressions once to be sure that you have it all correct.