Hi Jeff,
If I understand you, your concern is that by connecting a MIM cap directly to the pad, you are violating a classic ESD rule in which no gate oxides should be directly connected to a pad, but rather should be somewhat isolated by a secondary resistor and secondary ESD clamps (some people refer to this as a "CDM resistor" or "CDM protection", since it was first proposed by Maloney as a form of protecting gate oxides from CDM failures.)

So what to do with the MIM, do you need the secondary protection?

some ESD experts suggest me to use a 50ohm resistor connected in series with the MIM cap.  

The answer is convoluted....it depends on your process and the type of MIM your using.  Some MIMs have a very nice, thick and robust nitride layer, and can tolerate overvoltage stresses of 15-25V...in these case you may probably get away without using secondary protection, and thus keep up your performance by avoiding series resistance.  If you do this, I still strongly recommend secondary ESD clamps on the back side of your MIM.

ESD clamp? you mean to add off-nmos and off-pmos on the other node of MIM cap?  

TSMC .18 provide a relatively thick MIM cap, about 372A, whose break-down voltage is about 15-25v or higher as you mentioned, i think.

If your MIM is actually a very high performance, thin insulator, you may need to consider treating it as a gate-oxide and protect it as such...yes the resistance will hurt you, and you will need to tune the resistance to both meet the manufacturing needs of ESD and the performance needs of your product.

In the end, you will need to know your process, and it reliability windows, as well as what your product can allow.  I have many times used the robustness of a MIM cap as my ESD isolation, and its worked great, but in other processes, my MIM was nearly as delicate as my oxides and it was out of the question.

One way around this is if you can substitute a MOM cap (metal finger/overlap cap) for your MIM in this particular application.  Such a cap would be plenty robust to not worry about ESD.  But I do not know how big your cap needs to be and and so forth, but its something to consider.

yes, MOM has low capacitance density, meanwhile our process doesn't provid its modeling either.

I am assuming of course that you are using reasonable primary ESD protection, either provided for by the foundary or by some third party.

yes, we have another SCR on the PAD, but very small for high speed.

If I misunderstood your concern please let me know.
Stephen

Hi Jeff,
 OK, so I am very familiar with the MIM in TSMC's 0.18 process.  I myself have gotten away with using the MIM as the ESD isolation impedance, no resistor necessary.  It is a robust MIM.

(For future reference, isolation resistance can be anywhere from 10 ohms to 400 ohms to be effective; 50 ohms, 200 and 400 are the most common choice.  Below 50 you run risks but those risk are manageable in certain cases.)

That being said, I am concerned that you are using snapback based devices for this process (are you using TSMC's RF LVTSCR or some third party device?).  The dual diodes work really well and in many cases can provide not only comparative capacitance loading, but their capacitance is quite linear over large signal swings, the SCR approach is not.  This is just a comment.  If your using TSMC LVTSCR with the MIM, you should still be good.....beware I am making an off the cuff judgment here....you will want to do your own due diligence and dot your T's and cross your I's.  Make sure that SCR will trigger and clamp at voltages levels tolerable by the MIM.

By secondary protection, yes I meant either small secondary dual diodes, or secondary snapback devices; or as you stated it, additional off-nmos and off-pmos.

Good Luck Jeff!
-Stephen