The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 29th, 2024, 6:34am
Pages: 1
Send Topic Print
VCO behavior modeling (Read 5289 times)
bandpass
New Member
*
Offline



Posts: 4

VCO behavior modeling
Feb 22nd, 2009, 5:32am
 
I use the kundert's VCO modeling and find some problen when do simulation in Hspice.

The problems: the VCO works well under 10uS, but the output is wrong when tran simulation larger than 10uS.

 I don't know what's wrong?

you can get the result use attachment hspice netlist.

 Thanks,
Back to top
 
View Profile   IP Logged
pancho_hideboo
Senior Fellow
******
Offline



Posts: 1424
Real Homeless
Re: VCO behavior modeling
Reply #1 - Feb 22nd, 2009, 8:43pm
 
Your problem is not "Behavioral Models" at all. It is no more than simple and easy common usage of simulator.

bandpass wrote on Feb 22nd, 2009, 5:32am:
The problems: the VCO works well under 10uS, but the output is wrong when tran simulation larger than 10uS.
This is due to very very simple and easy reason.
You are trying to plot too many points(200u/1p=200Mpts).
In your environment, data points upto 10Mpts(=10u/1p) are permissible.

And you don't specify "delmax" in your netlist.

When you do transient analysis, you have to consider reasonable values setting about tstop, tstep, delmax, trise and tfall.
This is very common sense which is true for any vendor's simulator.

Modified vco.sp
Quote:
** Generated for: hspiceD
** Generated on: Feb 17 19:55:41 2009
** Design library name: beh_kundert
** Design cell name: PLL_usb_sim
** Design view name: schematic

.hdl "vco.va"

.TEMP 25.0

** Library name: beh_kundert
** Cell name: PLL_usb_sim
** View name: schematic
xi1 out in vco vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
*xi1 out in vco3_kundert *vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
v1 in 0 DC=1 *AC 1 PULSE 0 1.2 0 1e-9 1e-9 9e-9 20e-9
*i9 clk_fb div25_out divider1 vh=1.2 vl=0 vth=600e-3 ratio=2 dir=1 tt=1e-12 td=1e-12

.OPTION
*+    ARTIST=2
+    INGOLD=2
+    MEASOUT=1
+    PARHIER=LOCAL
*+    PSF=2
+    post = 1
+    probe
+    delmax = 0.1n       $ maximum internal time step


*.OP

*.TRAN 1e-12 200e-6 START=0.0
.TRAN 10n 200u START=0.0

* 200u/1p=200Mpts  <--- Your Setting
* 200u/10n=20kpts  <--- My Setting

.probe tran V(in) V(out)


.END

Back to top
« Last Edit: Feb 23rd, 2009, 7:52am by pancho_hideboo »  

vco.jpg
View Profile WWW Top+Secret Top+Secret   IP Logged
bandpass
New Member
*
Offline



Posts: 4

Re: VCO behavior modeling
Reply #2 - Feb 23rd, 2009, 4:39am
 
Thank you very much. The problems are resolved due to your advice.

Thank you.



pancho_hideboo wrote on Feb 22nd, 2009, 8:43pm:
bandpass wrote on Feb 22nd, 2009, 5:32am:
The problems: the VCO works well under 10uS, but the output is wrong when tran simulation larger than 10uS.
This is due to very very simple and easy reason.
You are trying plot too many points(200u/1p=200Mpts)

You have to consider reasoble value setting about tstop, tstep, delmax, trise and tfall.

Modified vco.sp
Quote:
** Generated for: hspiceD
** Generated on: Feb 17 19:55:41 2009
** Design library name: beh_kundert
** Design cell name: PLL_usb_sim
** Design view name: schematic

.hdl "vco.va"

.TEMP 25.0

** Library name: beh_kundert
** Cell name: PLL_usb_sim
** View name: schematic
xi1 out in vco vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
*xi1 out in vco3_kundert *vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
v1 in 0 DC=1 *AC 1 PULSE 0 1.2 0 1e-9 1e-9 9e-9 20e-9
*i9 clk_fb div25_out divider1 vh=1.2 vl=0 vth=600e-3 ratio=2 dir=1 tt=1e-12 td=1e-12

.OPTION
*+    ARTIST=2
+    INGOLD=2
+    MEASOUT=1
+    PARHIER=LOCAL
*+    PSF=2
+    post = 1
+    probe
+    delmax = 1e-10       $ maximum internal time step

*.OP

*.TRAN 1e-12 200e-6 START=0.0
.TRAN 10n 200u START=0.0

* 200u/1p=200Mpts
* 200u/10n=20kpts

.probe tran V(in) V(out)

.END


Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.