I have read the document of "modeling varactors" (http://www.designers-guide.org/Modeling/varactors.pdf.) and tried my best to reproduce the curve of Exhibited Capacitance(figure 2, p5).
However, I still could not get the same simulation result as figure 2.
All I could get is the expected capacitance.
Does anyone give me a netlist of this for my reference?
Thanks.

Thanks for your reply.

My test examples as attached. One is charge-based varactor model and the other one is the capacitance-based varactor model.
I expected to see the same result as the one shown in the document. Are there anything wrong? Could someone give an example?

By the way, the document mentioned that "A tell-tale symptom of this problem is that an anomalous DC current appears
to flow through the varactor. This problem does not occur if (2) is used.".
However, it shows the discrepency in the CV plot. This is also one of my questions.


test_varactor_c.scs
// varactor test circuit
simulator lang=spectre
include "varactor_c.scs" section=moscap
Vt (n 0) vsource mag=1
Xv (n 0) varactor
capacitanceInF ac freq=1/(2*M_PI) start=-2 stop=2 dev=Vt param=dc
save Xv:1

varactor_c.scs
//
simulator lang=spectre insensitive=yes
library test_varactor
section moscap
//
subckt varactor ( p n )
parameters c0=1p c1=0.5p v0=0 v1=1
cg ( p n ) bsource c=c0+c1*tanh((v(p,n)-v0)/v1)
ends varactor
endsection moscap
endlibrary

test_varactor_q.scs
// varactor test circuit
simulator lang=spectre
include "varactor_q.scs" section=moscap
Vt (n 0) vsource mag=1
Xv (n 0) varactor
capacitanceInF ac freq=1/(2*M_PI) start=-2 stop=2 dev=Vt param=dc
save Xv:1

varactor_q.scs
//
simulator lang=spectre insensitive=yes
library test_varactor
section moscap
//
subckt varactor ( p n )
parameters c0=1p c1=0.5p v0=0 v1=1
cg ( p n ) bsource q=c0*v(p,n)+c1*v1*ln(cosh((v(p,n)-v0)/v1))
ends varactor
endsection moscap
endlibrary test_varactor

Oh, you would be much better served by using Verilog-A rather than bsources. Bsources are very limited and have huge user traps like this one. With Verilog-A you can still fall into the user traps, but they are not so inviting. Furthermore, Verilog-A is a much richer capability. Knowing it is a very useful skill that can take you far.

-Ken