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Complex Analog/RF/DSP IC design tool/flow (Read 28432 times)
currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #15 - Apr 14th, 2009, 3:55am
 
 I included model file via Netlist Include block. Model file was a rfModels.scs.
 When I comment some models (pch , nch  and gaas) simulation was done.

Netlist:

 #ifndef inc_rfExmplTrain_ne600_ADS_schematic
#define inc_rfExmplTrain_ne600_ADS_schematic \
       inc_rfExmplTrain_ne600_ADS_schematic
; Library name: rfExmplTrain
; Cell name: ne600_ADS
; View name: schematic
define rfExmplTrain_ne600_ADS_schematic ( Pif Plo Prf )
simulator lang=spectre
crf (net33 Prf) capacitor c=10n
C1 (net51 0) capacitor c=1 * 0.6p
C2 (net49 0) capacitor c=1 * 0.6p
cif (net55 net27) capacitor c=10n
clo (net39 Plo) capacitor c=10n
cm (net27 0) capacitor c=4.7p
L1 (net51 net33) inductor l=3n
ldc (net41 net55) inductor l=10u
lm (net27 Pif) inductor l=470n
L0 (net49 net39) inductor l=3n
vcc (net41 0) vsource dc=5 type=dc
vdc_lo (net43 0) vsource dc=3.37 type=dc
vdc_rf (net45 0) vsource dc=2.3 type=dc
rl1 (net41 net55) resistor r=1K
r46 (net43 net49) resistor r=60
r45 (net65 net51) resistor r=30
r44 (net65 0) resistor r=450
q56 (net55 net43 net64 0) NPNupper area=1
q57 (net41 net49 net64 0) NPNupper area=1
q58a (net64 net45 net65 0) NPNlower area=1
q58b (net64 net45 net65 0) NPNlower area=1
simulator lang=ads
end rfExmplTrain_ne600_ADS_schematic
#endif
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #16 - Apr 14th, 2009, 5:55am
 
currant wrote on Apr 14th, 2009, 3:55am:
I included model file via Netlist Include block. Model file was a rfModels.scs.
When I comment some models (pch , nch  and gaas) simulation was done.
So your problem has been resolved ?

currant wrote on Apr 14th, 2009, 1:55am:
Now, I am  using evalution version of ADS2009 (Dynamic Link still exist)
As I said, ADS2009 is last version which support RFDE and Dynamic Link officially.

After ADS2009U2, RFDE and Dynamic Link might be still available, but it can not be officially supported.
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #17 - Apr 14th, 2009, 6:30am
 
  Yes, for this moment problem resolved. I worried about simulation with real PDK, but You already gave answer.

Quote:
After ADS2009U2, RFDE and Dynamic Link might be still available, but it can not be officially supported.

 It's not good.
 It seems, that I need more accurately select set of tools.
 Now, I know  litle bit more about Cadence RF Design Methodology Kit (there is Simulink co-simulation possible) - set of tools for this Kit is very expensive.
  Using GoldenGate + Ptolemy source/sink  looks like not complete system simulation way (may be I wrong).
 
 I will reread Your posts.

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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #18 - Apr 14th, 2009, 6:52am
 
currant wrote on Apr 14th, 2009, 6:30am:
Now, I know litle bit more about Cadence RF Design Methodology Kit (there is Simulink co-simulation possible) - set of tools for this Kit is very expensive.
You don't have to purchase "Cadence RF Design Methodology Kit" to do cosimulation between Spectre and Simulink.
With only Spectre licence, you can do cosimulation between Spectre and Simulink.

I don't use cosimulation between Spectre and Simulink although I have Spectre and Simulink.
Maybe if you use them, you could understand reason why I don't use it.

currant wrote on Apr 14th, 2009, 6:30am:
Using GoldenGate + Ptolemy source/sink looks like not complete system simulation way (may be I wrong).
You are right.
"Source" is no more than Vector Signal Generator to generate Digital Modulation Signal.
"Sink" is no more than Vector Signal Analyzer, BER Meter, Oscilloscope.

Currently you can not simulate true mixed signal interaction using Ptolemy in GoldenGate.

But if you write signal processing blocks using Verilog-D(SystemVerilog), you can do simulate true mixed signal interaction using NCsim in GoldenGate.
So I don't think this is problem because we have to write RTL finally.
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #19 - Apr 15th, 2009, 6:19am
 
Hi, pancho_hideboo.

 I've read many times Your very usefull posts, not only in this branch and briefly looked through  docs.    
 So, now I think I undestand why You want to insert FastSPICE in design flow. In my system I wanted to use (under master DT simulator) in design/verification process as far as possible envelop analysis and avoid transient analysis. But as soon as designer of block introducies Verilog-A model I must avoid hidden states independent of frameworks (ADE, ADS,Simulink ....). And in most cases I must use transient analysis. In my chip BandPass sigma-delta ADC is a core. And the core of it is verilog-a function z-transform . So I must use only tran analys when I verify the model of ADC in my system. And so there is no difference  what simulator (spectre, ADSSim, GoldeGate...) I am using.

  Is UltraSim - FastSPICE simulator?

  Quote:
But if you write signal processing blocks using Verilog-D(SystemVerilog), you can do simulate true mixed signal interaction using NCsim in GoldenGate.

After briefly reading userGuide of GoldenGate I don't undestand how we can use this sort of co-simulation? GoldenGate understand only Verilog-A.

 Many Thanks, pancho_hideboo.

PS. Your post about AWR MWO is great help in question of tools for top-down mixed/analog/RF IC design.
   
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #20 - Apr 15th, 2009, 6:56am
 
currant wrote on Apr 15th, 2009, 6:19am:
But as soon as designer of block introducies Verilog-A model
I must avoid hidden states independent of frameworks (ADE, ADS, Simulink ....).
I can't understand meaning of your sentence.
As I said, you don't have to care about hidden state of models in both Ptolemy and Simulink.

currant wrote on Apr 15th, 2009, 6:19am:
And in most cases I must use transient analysis.
In my chip BandPass sigma-delta ADC is a core. And the core of it is verilog-a function z-transform.
So I must use only tran analys when I verify the model of ADC in my system.
And so there is no difference what simulator (spectre, ADSsim, GoldeGate...) I am using.
Is UltraSim - FastSPICE simulator?
I don't use UltraSim although I can use it if I consume many tokens for MMSIM.

I want to introduce BDA's FastSpice in my design environment.
http://www.berkeley-da.com/index.htm
This transient simulator is most superior in current all commercial simulators.

currant wrote on Apr 15th, 2009, 6:19am:
After briefly reading userGuide of GoldenGate I don't undestand how we can use this sort of co-simulation?
GoldenGate understand only Verilog-A.
Being different from documentations of ADS(RFDE), documentations of GoldenGate are not opened for people who have no support contract.

"Mixed Signal transient co-simulations of RF and Verilog-AMS" was introduced in GoldenGate-4.2.
http://www.agilent.com/about/newsroom/presrel/2008/22apr-em08074.html
http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng&ckey=1374940&nid=-...

http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng&ckey=1507014&nid=-...
http://edocs.soco.agilent.com/display/gg432/GoldenGate+RFIC+Simulator+Release+No...

http://www.designers-guide.org/Forum/YaBB.pl?num=1232855139
http://www.designers-guide.org/Forum/YaBB.pl?num=1232220194/5#5

Cosimulation using Envelope and Verilog-AMS will be introduced this summer.
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #21 - Apr 16th, 2009, 2:17am
 
Hi, pancho_hideboo.

 Sorry for my persistence. I am trying to achieve as more as possible clearness before I will start the work with simulators.
 
pancho_hideboo wrote on Apr 15th, 2009, 6:56am:
As I said, you don't have to care about hidden state of models in both Ptolemy and Simulink.

 As I undestood You meant internal models/blocks of Ptolemy and Simulink. Simulink doesn't simulate Verilog-A/AMS models, it only can export RF block as a Verilog-A description.
 Ptolemy can simulate Verilog-A models only via co-simulation with ADSSim tran and envelope analysis, so all troubles of hidden states still exist. Is't it?
 
pancho_hideboo wrote on Mar 28th, 2009, 5:27am:
Here Agilent Ptolemy models can be imported into Cadence AMSD.

 As I undestand the nature of this, is very similar to source/sink import to GoldenGate.   Am   I right?

 Can You give me a link to ADS documents, where it is  describe  how I must convert netlist  from spectre in order to use it with ADSSim? Do You correct netlist by hand on?
 
 About BDA's FastSpice. It seems very good, can You provide me links for  forum topics about about BDA's FastSpice? Is it understand spectre models? Is it easy build in ADE framework?

  pancho_hideboo wrote on Apr 15th, 2009, 6:56am:
Cosimulation using Envelope and Verilog-AMS will be introduced this summer.

   So, will we not suffer from hidden states of couple of Verilog-A blocks  and envelop analysis?

 Many thanks, pancho_hideboo.
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pancho_hideboo
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #22 - Apr 16th, 2009, 3:23am
 
currant wrote on Mar 28th, 2009, 6:56am:
I thought about MATLAB, but it allows to work only on Verilog-A model level,
currant wrote on Mar 28th, 2009, 7:32am:
About MATLAB. As I know, MATLAB can work with Verilog-A models, may be I wrong.

MATLAB are different from Simulink.
Both MATLAB and Simulink can't understand Verilog-A and can't treat Verilog-A.

currant wrote on Apr 16th, 2009, 2:17am:
Simulink doesn't simulate Verilog-A/AMS models,
Right.

currant wrote on Apr 16th, 2009, 2:17am:
it only can export RF block as a Verilog-A description.
Where and what can it export ?

currant wrote on Apr 16th, 2009, 2:17am:
Ptolemy can simulate Verilog-A models only via co-simulation with ADSSim tran and envelope analysis,
No. There is a misunderstanding point.
In cosimulation, Verilog-A models and Analog part of Verilog-AMS are treated by ADSsim not Ptolemy.
Simulink models are treated by Simulink not by MMSIM(Spectre).
Ptolemy models are treated by Ptolemy by neither MMSIM(Spectre) nor ADSsim.

currant wrote on Apr 16th, 2009, 2:17am:
so all troubles of hidden states still exist. Is't it?
If you write model which have hidden state by Verilog-A, hidden state problems exist for ADSsim.

Again you don't have to care about hidden state of models in both Ptolemy and Simulink, because they are not treated by ADSsim or MMSIM(Spectre).

currant wrote on Apr 16th, 2009, 2:17am:
pancho_hideboo wrote on Mar 28th, 2009, 5:27am:
Here Agilent Ptolemy models can be imported into Cadence AMSD.
As I undestand the nature of this, is very similar to source/sink import to GoldenGate. Am I right?
Right.

currant wrote on Apr 16th, 2009, 2:17am:
Can You give me a link to ADS documents, where it is describe how I must convert netlist from spectre in order to use it with ADSSim?
Do You correct netlist by hand on?
I can't understand meaning of your sentences.
 
currant wrote on Apr 16th, 2009, 2:17am:
About BDA's FastSpice. It seems very good, can You provide me links for forum topics about about BDA's FastSpice?
I can't understand meaning of your sentence.

currant wrote on Apr 16th, 2009, 2:17am:
Is it understand spectre models? Is it easy build in ADE framework?
Yes for both questions.
Contact BDA's distributor or sales.
http://www.berkeley-da.com/cont/index.htm

currant wrote on Apr 16th, 2009, 2:17am:
pancho_hideboo wrote on Apr 15th, 2009, 6:56am:
Cosimulation using Envelope and Verilog-AMS will be introduced this summer.
So, will we not suffer from hidden states of couple of Verilog-A blocks and envelop analysis?
No. Hidden state problems of Verilog-A or Analog portions in Verilog-AMS exist for GoldenGate.

But you don't have to care about hidden state of Verilog-D or Digital portions in Verilog-AMS because they are treated by NCsim not GoldenGate.

In Mixed-signal systems, you need mixed analysis of following three domains.

 - CT(Continuous Time) ; Tran, Envelope simulator such as ADSsim, GoldenGate, MMSIM(Spectre), MMSIM in AMSD
 - DT(Discrete Time) ; SDF/TSDF simulator such as Ptolemy, Simulink, SPW(CoWare SPD), SystemVue, etc.
 - DE(Discrete Event or Event Driven) ; NCSim, VCS, ModelSim

Domain or Analyis Engine where you have to care about hidden state is only CT(Continuous Time).

Verilog-A or Analog portions in Verilog-AMS are treated by CT analysis engine.
Verilog-D or Digital portions in Verilog-AMS are treated by DE analysis engine.
Ptolemy models and Simulink models are treated by DT analysis engine.
Models of SPW(CoWare SPD) can be also treated by DE analysis engine.

I don't think your application aim for RF intensively.
I don't think Ptolemy models are needed for your applications.
Also I don't think you need Cadence NCsim for your applications.
So you don't need Cadence AMSD.

So for your purpose, I recommend you to use cosimulation between Cadence Spectre and Mathworks Simulink.

If you already have Cadence Spectre and Mathworks Simulink, you can easily do cosimulation for your purpose.
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« Last Edit: Apr 16th, 2009, 8:28am by pancho_hideboo »  
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #23 - Apr 16th, 2009, 4:46am
 
pancho_hideboo wrote on Apr 16th, 2009, 3:23am:

currant wrote on Apr 16th, 2009, 2:17am:
it only can export RF block as a Verilog-A description.
Where and what can it export ?

   This is my bad English, therefore there is a fragment from datasheet of RF toolbox:
   "RF Toolbox software lets you export a Verilog-A model of an rfmodel object. The toolbox provides one rfmodel object, rfmodel.rational, that you can use to represent any RF component or network for export to Verilog-A."

 pancho_hideboo wrote on Apr 16th, 2009, 3:23am:
currant wrote on Apr 16th, 2009, 2:17am:
About BDA's FastSpice. It seems very good, can You provide me links for forum topics about about BDA's FastSpice?
I can't understand meaning of your sentence.

 I meant, Are here (in this forum), topics about BDA FastSPICE?

  pancho_hideboo wrote on Apr 16th, 2009, 3:23am:
currant wrote on Apr 16th, 2009, 2:17am:
Can You give me a link to ADS documents, where it is describe how I must convert netlist from spectre in order to use it with ADSSim?
Do You correct netlist by hand on?
I can't understand meaning of your sentences.

  I meant, how can/must I modify spectre netlist in order to use it with ADSSim. Is there automatic procedure, or I will need do it by hand.    I will try it and after, if I have problem, ask about this.

 Your help was/is invaluable.
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #24 - Apr 16th, 2009, 4:50am
 
currant wrote on Apr 16th, 2009, 4:46am:
"RF Toolbox software lets you export a Verilog-A model of an rfmodel object.
The toolbox provides one rfmodel object, rfmodel.rational, that you can use to represent any RF component or network for export to Verilog-A."
You are misunderstanding.

First, this is Toolbox of MATLAB not Blockset of Simulink.
Second, this is not for cosimulation.
This is just translation of mathematical equations for nonlinear input/output characteristics of MATLAB to Verilog-A.

currant wrote on Apr 16th, 2009, 4:46am:
I meant, Are here (in this forum), topics about BDA FastSPICE?

http://www.designers-guide.org/Forum/YaBB.pl?num=1183646486/11#11

currant wrote on Apr 16th, 2009, 4:46am:
I meant, how can/must I modify spectre netlist in order to use it with ADSsim.
What do you refer as "it" ?

currant wrote on Apr 16th, 2009, 4:46am:
Your help was/is invaluable.
I don't append any reply for your all posts any more.
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« Last Edit: Apr 16th, 2009, 8:30am by pancho_hideboo »  
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currant
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Re: Complex Analog/RF/DSP IC design tool/flow
Reply #25 - Apr 16th, 2009, 5:11am
 
pancho_hideboo wrote on Apr 16th, 2009, 4:50am:
currant wrote on Apr 16th, 2009, 4:46am:
"RF Toolbox software lets you export a Verilog-A model of an rfmodel object.
The toolbox provides one rfmodel object, rfmodel.rational, that you can use to represent any RF component or network for export to Verilog-A."
You are misunderstanding.

First, this is Toolbox of MATLAB is not Blockset of Simulink.
Second, this is not for cosimulation.?

Yes, I did some mistake, but in RF Blockset doc there is no "Verilog-A" word at all. Now, I clearly undestand: there is no Verilog-A cosimulation nor Simulink nether MATALB.)


pancho_hideboo wrote on Apr 16th, 2009, 4:50am:
currant wrote on Apr 16th, 2009, 4:46am:
I meant, how can/must I modify spectre netlist in order to use it with ADSsim.
What do you refer as "it" ?

netlist.
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