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Importing Verilog using Verilog In (Read 1765 times)
jefkat
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Importing Verilog using Verilog In
Apr 29th, 2009, 8:52am
 
Hi,
 I imported a big hierarchical verilog design into cadence using 'Verilog In' from CIW. The problem is that the generated functional views dont have include statements. As a result my
ams simulator compains about the defines that were being
referenced.
  Any help?
 shaf
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