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Dipankar Community Member Offline Posts: 59	buffer in LDO Nov 19^th, 2009, 9:10am Want to design a buffer interposed between error amplifier and PMOS pass device. (Iload being 50 mA pass device is huge) . But vin = 1.2 V. So can't use a simple source follower because of voltage level shift. Can some one hint at some other approach ?
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: buffer in LDO Reply #1 - Nov 20^th, 2009, 6:08am hi, whats the problem with big device man,there are many low jitter plls with ring oscillators are drawing 30 to 40ma, you can proceed, if you want to put a buffer again you have to compensate loop. This will give very bad PSRR. Thanks, Rajasekhar.
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Mayank Community Fellow Offline Posts: 334	Re: buffer in LDO Reply #2 - Nov 20^th, 2009, 6:45am Thanx raja, That's exactly what i needed to know....that there exist low jitter plls which take powers up to 30 - 40 mA with ring osci's on 1.2V supply....& that my design is not so bad after all.....But about how low jitter & what osc freq.+comparison freq. pair are you referring to at this much power burnout ?? --mayank.
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: buffer in LDO Reply #3 - Nov 20^th, 2009, 7:41am hi, it's around 6.2G, but here actually ring oscillator driving many phase mixer. Thanks, rajasekhar.
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Dipankar Community Member Offline Posts: 59	Re: buffer in LDO Reply #4 - Nov 20^th, 2009, 6:42pm Dear Sirs, Please don't diverge from the topic under this thread. The motivation behind the buffer in the LDO (after the 1st gain stage) is not enhancing driving capability but impedaance transformation so that the high output impedance of the 1st stage amplifier does not see the high capacitance of the pass device.
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Mayank Community Fellow Offline Posts: 334	Re: buffer in LDO Reply #5 - Nov 20^th, 2009, 8:04pm Correct me if i am wrong dipankar, but isn't the error amplifying Loop supposed to have as low BW as possible....So Increased cap should reduce BW & improve PM of the loop.... --mayank
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: buffer in LDO Reply #6 - Nov 21^st, 2009, 8:58am hi Dipankar, the motivation behind buffer is mainly for driving capability,not impedance..just check impedance, i feel its same in both cases. @mayank: how can say error amp bw is low? it depends on the psrr profile you want. Thanks, Rajasekhar.
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Mayank

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Re: buffer in LDO
Reply #7 - Nov 26^th, 2009, 7:45am

Hello,
Sorry for the delay....was busy in past few days...

@ raja : I believe that more the error amplifier BW, more the noise introduced at the Vbias node (gates) of the PMOS transistors...
Lemme explain it this way....Suppose opamp has some finite UGB Fo......It will process all noise elements in supply below Fo as small signal input and vary the output accordingly.....But all high frequency noise above Fo will not change the output of the opamp..Which is what we desire....
This way if Error Amplifying Loop BW is very Low, we will get even better supply noise rejection

Quote:

it depends on the psrr profile you want.

Could you explain it further ??

--mayank

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: buffer in LDO Reply #8 - Nov 26^th, 2009, 9:56am hi mayank, what i want to say is opamp BW is mainly decided by AC psrr....... Thanks, Rajasekhar.
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