Hello,
Sorry for the delay....was busy in past few days...
@ raja : I believe that more the error amplifier BW, more the noise introduced at the Vbias node (gates) of the PMOS transistors...
Lemme explain it this way....Suppose opamp has some finite UGB Fo......It will process all noise elements in supply below Fo as small signal input and vary the output accordingly.....But all high frequency noise above Fo will not change the output of the opamp..Which is what we desire....
This way if Error Amplifying Loop BW is very Low, we will get even better supply noise rejection
Quote:it depends on the psrr profile you want.
Could you explain it further ??
--mayank