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ldo design : body bias to lower vt of pass device (Read 1391 times)
Dipankar
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ldo design : body bias to lower vt of pass device
Nov 19th, 2009, 9:23am
 
Dear All,
              I want to know how safe is the technique of reducing VTH of the PMOS pass device by  body bias. Even if I make sure for the highest load current  the vsb < 300 mv still I'm little affraid to use this.
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With Thanks and Regards,
Dipankar.
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Mayank
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Re: ldo design : body bias to lower vt of pass device
Reply #1 - Nov 19th, 2009, 10:24am
 
Hello Dipankar,
                      As long as you ensure the bulk-source junction doesnt cross the Potential Barrier voltage of the p-n jnxn, You can use Fwd Body-Bias to reduce Vt.....
    But keep in mind,
1.  there's a limit to which you can reduce Vt using this technique....
2.  You would need Triple-Well technology -- costly.
3.  You have to ensure that across PVT, your bulk-source jnxn doesnt become forward-biased.
4.  keep you bulk-source bias programmable to again bring back Vt to normal values while in Power-Down Stage otherwise leakage current can increase.
5.  Ensure your models are reliable when you are using these kind of risky techniques...

I provided you the advantages & disadvantages....Weigh the pros & cons yourself & then decide.

--mayank
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