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Mayank Community Fellow Offline Posts: 334	Oscillators - Phase Noise Degradation Nov 26^th, 2009, 6:29am Hi, I have designed a CML Voltage-Controlled Oscillator in 65nm process. Without the bias ckt (using ideal voltage source), the Oscillator shows -55 dBc @ 10kHz..... How much degradation can i expect in this Phase Noise when i add a bias ckt with Replica Biasing scheme ?? -- thanx mayank.
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Oscillators - Phase Noise Degradation Reply #1 - Nov 26^th, 2009, 4:53pm tough to say - sounds like the best thing you can do is get it down to transistors and run Spectre PSS and Pnoise analysis. jerry
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Mayank

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Re: Oscillators - Phase Noise Degradation
Reply #2 - Nov 27^th, 2009, 1:00am

Hi Jerry,
Already carried out a PSS/PNOISE simulation on one of my designs...Got +ve Phase Noise ie > 0 dBc values

......Had a long Discussion with one of the senior members, Pancho_hideboo in the rf_simulators forum starting from http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/0#8

...Seems like none of the simulators are able to give correct results for Phase noise below the line-width of the oscillator. Any fix for this ??

--mayank.

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pancho_hideboo

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Re: Oscillators - Phase Noise Degradation
Reply #3 - Nov 27^th, 2009, 2:09am

Mayank wrote on Nov 27^th, 2009, 1:00am:

...Seems like none of the simulators are able to give correct results for Phase noise below the line-width of the oscillator. Any fix for this ??

I think an integration without including suspicious frequency region is still enough useful for evaluation of jitter or phase noise.

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« Last Edit: Nov 27^th, 2009, 10:53am by pancho_hideboo »

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