I assume your ADC is not undersampling. Is this right ?
Mayank wrote on Nov 27th, 2009, 12:00am:Can such a clock with an average freq around 179.2 MHz but not exact, be used as a SAMPLING CLOCK for ADC ???
Solution 1 might be possible for your purpose.
Assume IF signal is downconverted from RF by mixing with Fractional PLL based LO.
Then assume ADC sampled by true 179.2MHz.
This might be equivalent to the following.
- IF signal is downconverted from RF by mixing with integer PLL based LO.
- ADC sampled by Fractional PLL based 179.2MHz.
I think reasonable estimation of SNR degradation due to sampling jitter is required for further proceeding.