Hello RDX,
On a standalone basis, you can simulate your PFD so that the UP & the DNbar or UPbar & DN signals math exactly....ie transition at vdd/2.
The Best way to characterize Phase-detector ckt of a PLL is to plug the PFD and Charge-Pump together.
1. Give two signals on input freq and fed-back Freq with a certain difference in Time-period & that difference as the delay between the clocks transitions. ---> The idea is to basically produce transitions with decreasing/ increasing difference b/w ref. freq node & PLL fed-back node.
2. Now measure the CPUMP current corresponding to each commparison. You will get a staircase kind of response...
3. This will help you estimate the gain of your P-D ckt as well as Static Phase Error.
4. If you want to obtain the gain plot of PD ckt, vary the delay b/w the two clocks at ref & PLL fed-back node and measure the Cpump current o/p. Plot cpump current o/p against the phase error (360deg * delay / Tcomparison) -- you will obtain a K
PD plot as shown in books...My belief is that you however generally dont need that plot.
thanx
mayank.