jbdavid
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I've not (yet) read the article.. but as a practitioner in this area, I'll say that you're correct. Parasistic coupling effects, like gate delays, are not part of the domain of functional verification, and you do need OTHER analyses to find these issues. The point of functional verification is to make sure to catch the stupid connection issues that would prevent you from running the first part on the test bench to discover that you might have a parasitic issue. Functional verification is NOT going to find this issue, but it will catch most of the REST of the design bugs so that when you do run that transistor extracted simulation, you can let it run to the point where the subtle issues can be identified. Its really hard to do that, if there are 20 design bugs to find and fix in a 10day simulation, unless you have a great foosball table, and six months of funding to burn. (imagining that once in a while you'll be able to fix two bugs before the next run.)
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