Mayank
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Hi all, I am attaching a graph showing Frequency , current & Resistance variation with Vcontrol for a CML Ring Oscillator. PROBLEM :--- Frequency curve vs. Vcontrol is not MONOTONIC. Around Vcontrol = 500mV, we reach the turning point (or the point of inflation as some mathematicians would say :( ). My Point is that i want my tuning range to be the upper half because since the current increases, Phase Noise is almost constant what i design for. Is there some way i can prevent my Vcontrol from going below 500mV as the PLL Loop settles ? I am afraid that during the locking process, vcontrol might fall below 500mV and PLL can settle on the left side of the graph(lower vcontrol) [img][/img]
regards, Mayank.
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