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Phase margin estimation for switched capacitor circuits (Read 4154 times)
shaikh_sarfraz
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Phase margin estimation for switched capacitor circuits
Jan 21st, 2010, 4:51am
 
Hi,
I want to find the phase margin of a switched capacitor based voltage regulator(buck type). Switching frequency of 1MHz.

I found that we can use PSS+PAC analysis for this.
However once I do PSS+PAC analysis, I can get the phase plot of the carrier and other harmonics.

If this is the correct approach then how can we extract the phase margin from the PAC analysis?

Best Regards
Sarfraz
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pancho_hideboo
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Re: Phase margin estimation for switched capacitor circuits
Reply #1 - Jan 21st, 2010, 5:44am
 
Your questions are no more than usage of very specific vendor's simulator.
There is no issue related to "RF Measurement".
Please post to "Simulator's Board" not "Measurement's Board".

Your following post is also not related to "Measurement".
http://www.designers-guide.org/Forum/YaBB.pl?num=1262097621

What vendor's simulator do you use ?
There are many simulators which have analyses called as PSS, PAC and Pnoise.

If you use Cadence Spectre, use PSS/PSTB.
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« Last Edit: Jan 21st, 2010, 8:07am by pancho_hideboo »  
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shaikh_sarfraz
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Re: Phase margin estimation for switched capacitor circuits
Reply #2 - Jan 21st, 2010, 8:51am
 
thanks for the help.........pss/pstb works
I am indeed using cadence spectre rf.

And sorry for posting it in the wrong section.

Best Regards
Sarfraz

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