Hello All,

I am looking for some info. regarding the "percentage of parasitic capacitances associated with the capacitors" realized in recent nanometer CMOS nodes. (MIM caps, etc.) Does anyone know a good reference?

Any help is appreciated.

thanks,
ali

analog_ali wrote on Feb 8^th, 2010, 8:00pm:


The percentage (i.e. ratio) of parasitic capacitance with respect to the total net capacitance for intended capacitors depends greatly on the following factors:

1. Capacitor type - MOS, Poly-to-Poly, MIM, MOM, etc.
2. Size of the capacitor (spatial dimensions as well as capacitance value)
3. Layout of the circuit that interconnects and/or shields the capacitors.

This percentage may range anywhere from ~0.1% up to ~50%.

For example, a typical value of capacitance density for MIM capacitors is ~1fF/um2. Design rules vary, but typically the minimum size of the capacitor is a few squared microns. So, a minimum capacitance value of a unit capacitor is a few fF - and hence parasitic capacitance of the nets connected to the capacitor plates can easily be comparable to the intended capacitance value.

What frequently matter is not the absolute value of parasitic capacitance, but the capacitance mismatch that is induced by the parasitics. The problem is that very often "standard" parasitic extraction tools (or PDKs provided by foundries) do not provide sufficient accuracy for capacitance mismatch analysis.

Berti wrote on Feb 16^th, 2010, 11:51pm:


"typical" with "~" means "order of magnitude". 4 fF/um2 falls into that category as well (although this value seems to be on the high side).

My main point was not to quote a specific value of MIM capacitor density, but to point out a fact that the minimum MIM/MOM/PIP/... capacitor value (as defined by design rules) is comparable to parasitic capacitance value.