Hello,

I'm trying to write the code of a pwm generator in VHDL. The entity "pwm_generator" takes :
duty value as input,
frequency and number of step (for one period) as generic parameters
It should return a pwm signal depending on the duty value.

My problem comes since I'm trying to make it as generic as possible. Then I try to calculate a clock period with the generic parameters (frequency, nb_of_steps and duty) and I want to use this result as a parameter of a wait instruction. In this case, the simulator is blocked in infinite loop as he waits 0.0 sec in my loop.

Is there a simple solution for this problem ? (can we force the calculation of v_delay ??)

Thanks

P.C

entity pwm_generator is
     generic (
           cst_nb_step : natural := 255 ;
           frequency : natural := 40000
           );
   port(
           duty_value : in natural ;
           pwm : out std_logic
           );
end entity pwm_generator ;

architecture beh of pwm_generator is

signal s_clock : std_logic := '0' ;
signal s_pwm : std_logic := '0' ;
signal s_delay : real := 0.0 ;

     
begin

process
variable v_delay : time := 500 us ;
     begin
           v_delay := (1/frequency/cst_nb_step * 1 sec ) ;
                 s_clock <= not(s_clock) ;
                 wait for v_delay ; -- works correctly with 500 us value
end process ;
     
process(s_clock)
variable counter, ratio :  natural := 0 ;
     begin
           ratio := ( duty_value * cst_nb_step / 100 ) ;

     if (counter /= 255) then
           if (counter >= ratio) then
                 s_pwm <= '0' ;
           elsif (counter < ratio) then
                 s_pwm <= '1' ;
           end if ;
           counter := ( counter + 1) ;
     elsif (counter = 255) then
           counter := 0;
           s_pwm <= '1' ;
     end if;      
end process ;

pwm <= s_pwm ;

end architecture beh ;