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Matching Delay Paths (Read 4421 times)
AnalogDE
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Matching Delay Paths
Apr 21st, 2010, 10:37am
 
Hi all,

I'm working on matched delay paths for a high speed i/o interface. Because of area constraints we cannot match metal routing lengths.  We are looking into the following scheme below:

Could this scheme work?  I'm worried about the delays tracking with process variation
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love_analog
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Re: Matching Delay Paths
Reply #1 - Apr 22nd, 2010, 4:24pm
 
If I understood your question correctly, this will not work.

Can you perhaps serpentine the short wire to make it match the long wire.
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AnalogDE
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Re: Matching Delay Paths
Reply #2 - Apr 22nd, 2010, 5:38pm
 
No, we don't have the room available to serpentine the short routes....

This is a hard problem, because the long route is 4000um, the short one is 500um and the delays need to be within +/- 200ps..  Can you think of any other schemes?

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love_analog
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Re: Matching Delay Paths
Reply #3 - Apr 26th, 2010, 10:41am
 
Anything else you do will always have this issue that you may be able to nominally match but over skew you may have issues. In addition, the fab might not model that correctly so your silicon will not match sim. Most fabs do not model interconnect skew that well.
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loose-electron
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Re: Matching Delay Paths
Reply #4 - Apr 27th, 2010, 12:32pm
 
put in a phase shift interpolation system and do a phase alignment and calibration routine.

Think string of inverters with a mux to pick the delay.

Or, synchronize using phase shifted clock and then re-sync in phase.

Try to adjust metal lines to compensate for variance in transistors will come up to bite you.

Serpetine path balancing is a possible improvement as well, and yes you can fiit it if you want (willing to wager?)

Wink

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Jerry Twomey
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