Quote:Right.
But from practical point of view, there is no remarkable affects for PLL characteristics at all, as far as voltage change is small and static.
Agreed. But then all you are doing is using an digital Calibration of FB resistor over an Analog Loop.
MOSMAN initially quoted :
Quote:the noise will be introduced if analog control loop is used. so the digital method is used.
That Analog Loop is very much there.
All you are doing is Calibrating your output voltage, but the loop which regulates your FB voltage is unchanged. Hence, the noise introduced in unchanged.
So, the noise from the Analog Loop is very much there, since the Loop is present.
As far as question of Digital Stepping is concerned,
Quote:Actually I change supply voltage from 1450mV to 1650mV by digital adjustment of feed back resistor ratio in linear regulator.
For such small voltage change, there is no remarkable change of bandwidth and gain of feedback loop.
And I can't observe any degradation of PLL characteristics as far as voltage change is static.
As we both said, it's not gonna unlock the PLL.
You are simply over/under driving the VCO, or in other words, varying oscillator VDD, so as to vary the output Frequency by a factor of Kpushing.
VCO can also be calibrated in other ways, like bands in I_tail_current, Cap load on osc nodes, etc. etc.
you are using VDD stepping, which is perfectly fine, is one of them.
Hence, MOSMAN,
you can use digitally trimmed voltage supply from an Analog Linear Regulator.
BUT the noise from the Analog Loop will be present as the Loop itself is there.--
Mayank.