aaron_do,
Use the n-port to simulate the inductor.
Place the n-port in a separate schematic view call it schematic_ind for example. then when you simulate set your switch viewlist in your simulation environment options to have schematic_ind before schematic. Or if you are familiar with the cadence hierarchy manager use that view in the config. you still will have a schematic view but it will only contain the pin names.
To handle the inductor in LVS is a separate step. First off an inductor without any special recognition layers in LVS is basically a short. So you will need to figure out how to resolve this, you may want to get some cad support on this, but here is what I typically do. Basically you need to identify in your pdk a layer that either acts as an LVS ignore or if your pdk has a metal resistor place it in your schematic and layout thus breaking up the shorted pins. if your inductor has three terminals then you will need at least two metal resistors. The metal resistors can be small remember it's only needed to remove the short.
Finally, if you plan to do this often you may want to work with your cad group to define a fool proof methodology moving forward. The reason is that of the two methods of LVS'ing I described above both can be jeopardized by carelessness during the layout. For example if a piece of extraneous metal is accidentally inserted into the region where the inductor resides and shorts out a turn or two and is not caught through visual inspection then it will be LVS clean, but desired performance will be incorrect.
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