See http://www.designers-guide.org/Forum/YaBB.pl?num=1165836451/2#2.

Whilst various synthesis tools have been created for specific classes of circuits, there aren't really any good general solutions. Years ago I wrote (along with some colleagues) a switch capacitor filter synthesis tool, which worked pretty well - but it was targeted at one specific type of circuit.

So normally it needs a designer to "synthesize" the design from a high level spec (or model) to transistor level (of course, you may be able to build the design from existing blocks such as opamps, data converters, comparators, etc).

The closest approach that has been reasonably successful is using optimization to size the design once the topology has been developed. This is mainly beneficial in terms of design centering and yield improvement though (and relies on you capturing the appropriate measurements and specifications to ensure that the optimizer is sufficiently well constrained).

Regards,

Andrew.

You need to hand craft the design. There's no push button to convert from a behavioural model to a transistor level design.

You should read some books on Analog Design to get a good idea of the process.

Best Regards,

Andrew.

Many attempts have been made to do automated analog design. Except for extremely limited cases of specific circuits, all have failed.

Going from RTL Verilog to a digital synchronous chip has largely been automated.

Not the case for analog design. If you have not done analog design it is time to go back to school in this area to become familiar with the issues involved.

Doing a Verilog AMS model of a converter is fairly straightforward, but gettting the design functional at the transistor level is orders of magnitude more complex.

Adding to the confusion, some of the tools that were developed to do automated analog design failed to recognize many of the variables that were important in making the design viable. One company burned huge amounts of venture capital with an outcome that allowed the automated design of op-amps. However, they were fixed in architecture, and the results were neither size or power optimized.

Not sure when computers are going to make this are obsolete, but its not on the horizon as of yet. The changing parameters associated with CMOS geometry changes has made the process even more difficult. Techniques to optimize become a moving target.

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