Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jun 2
nd
, 2023, 2:42pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Modeling
›
Transmission Lines and Other Distributed Devices
› distributed interconnect paramter calculation in cadence
‹
Previous topic
|
Next topic
›
Pages: 1
distributed interconnect paramter calculation in cadence (Read 7621 times)
sujeetkumarmehta
New Member
Offline
Posts: 2
nagpur
distributed interconnect paramter calculation in cadence
Feb 22
nd
, 2011, 1:04pm
I wanted to know how to define distributed transmission line parameter in cadence ? can it be done with mt line ?
Back to top
IP Logged
Larry_80
Community Member
Offline
Posts: 61
Re: distributed interconnect paramter calculation in cadence
Reply #1 -
Aug 16
th
, 2011, 9:32pm
why don't u just use the transmission line equivalent models i.e L R and C if you have them?
Back to top
IP Logged
rfcooltools.com
Senior Member
Offline
Posts: 159
Re: distributed interconnect paramter calculation in cadence
Reply #2 -
Sep 7
th
, 2011, 6:18pm
sujeetkumarmehta,
if you have a single line use the tline in the analog lib. There are more entries in the form than needed to make the model work. Typically I just enter characteristic impedance and length. The same applies to the mtline.
http://rfcooltools.com
Back to top
IP Logged
loose-electron
Senior Fellow
Offline
Best Design Tool =
Capable Designers
Posts: 1638
San Diego California
Re: distributed interconnect paramter calculation in cadence
Reply #3 -
Oct 29
th
, 2011, 6:08pm
consider the possiblitity of lumped elements in a cascaded chain. Frequently this is more accurate than doing the transmission line model.
Back to top
Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
»» Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2023
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.