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Flexible pin naming convention for cells in Cadence Schematic Composer (Read 2970 times)
nara
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Flexible pin naming convention for cells in Cadence Schematic Composer
Apr 20th, 2011, 5:02pm
 
Dear group members,
This is my first post.
I would like to know the most compact and flexible way of expressing pin and bus naming convention, for a scenario as described:
A block(cell) takes in 32 inputs of 16 bit bus width (and produces output, say similar as input).
It will be highly laborious task to give names of the pins as in1<15:0>, in2<15:0>, in3<15:0>,....in32<15:0> and so on..
And instead of 32 input pins is there a way to have just a single pin of 32*16 bit wide.

Any help in this regard is laudable.
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