Hi all!

I am afraid i'm seriously new to analog design but have got my first assignment to designing of a fully differential folded-cascoded OTA. Can someone kindly guide me, or give some link to a step by step design tutorial? I'm implementing a configuration with a pmos differential input stage.

Thanks for help!

Thanks.

I am trying to do simulations on Cadence using UMC 180 nm technology. kp=180, kn=70uA/V.

My circuit is a pmos diff input stage. It has a Output CMFB circuit also, and I don't know at all how to go ahead with it.

Can you please help?

I don't know why this is made to be such a big deal by the various authors. gm/Id is so "non physical." On the other hand 2*Id/gm is about Vgs-Vt, which is just the overdrive of the transistor. It is how much headroom the MOS needs. It is what you need to consider to fit the design between the rails. It is physical. gm/Id is just a number that needs further adjustment to make it useful. That is to say, to convert it to Vgs-Vt. So why not start with Vgs-Vt?

For design, I use the cadence parameter vdsat as a proxy for Vgs-Vt. The first pass at a design is pretty simple:
1) Set your diff pair and cascode vdsat to 150mV to maximize its gm (less vdsat than that gives diminishing returns as it enters weak inversion)
2) Set the current mirror vdsat as large as headroom will allow (say 300 mV). This will minimize its gm.
3) If you have a second stage, maximize its gm by setting vdsat=150mV.
4) Cascode devices usually have the same width as the device it is cascoding, but a shorter length.

Note that gm ~2I/(Vgs-Vt). (Or I/nUt if in weak inversion). Use that to figure out what your tail current needs to be to get the bandwidth or noise that you need. Similarly the output stage current is determined by the gm required to push the 2nd pole out enough to give phase margin.