aaron_do
|
So now you asking the question for a common-source NMOS with a PMOS load? Can I assume the PMOS transistor is in saturation?
OK in this case, the simplified model doesn't work (i.e. the one where IDS is independent of VDS). In this case, any drain voltage which allows both NMOS and PMOS to be in saturation will be a correct solution to the problem. However, for a more realistic, but still simple model, IDS depends on VDS to a certain degree and this is shown in most basic analog texts (simplist reason is due to channel-length modulation). The easiest way to calculate the value of the drain-voltage of the transistor is to use a load-line curve. I drew an example below, but I kind of did it in a hurry, so sorry for the mess. Anyway, you can find this kind of example in some basic texts (See for example, Section 4.9 in Microelectronic Circuits by Sedra and Smith).
hope it helps, Aaron
|