Hi there,

I am designing an ASIC that uses a memory IP from my fab. The design is a mixed-signal chip, but I use the digital-on-top workflow, so most of the chip finishing is done on Encounter. However, I still need to fine tune the layout in Virtuoso.

Here's is the problem: in virtuoso, I don't have the layout view for the memory block (not even the abstraction layers, e.g. metals, blockages). Is it possible to import an abstract LEF cell into Virtuoso IC 5.10.41?

I would like to perform some visual inspections on virtuoso around the memory block, before tape-out.

Thanks.
C.

Thanks, import/lef: it goes without saying!

Worked just fine.

Cheers,
C.