Hello everyone:

       I have a question about PLL reference clock.
       if we have two reference clock, the phase noise spec and frequency are the same and the only difference is the output clock power. use these two clock as one PLL reference, how will the PLL performance change?

       PS: I think that different output power and the same phase noise
              ->the absolute power of phase noise will be different
              ->the PLL output phase noise caused by reference will be different
              ->but this will contradict to Ken's paper "predicting the phase noise and jitter of PLL-Based frequency synthesizers"


Thanks!

I'm sorry I did not explain this question clearly.
if we have two clocks, their output amplitudes are different(eg. one is 1V and another is 2V) but the phase noise are the same(eg. -100dBc/Hz@10K, -120dBc/Hz@100K, -150dBc/Hz@1M).
then we use these two clock as two PLL's reference respectively, the other part of these two PLL are the same to each other.
how about these two PLL output phase noise? (same or different?)

Thanks for your time~

Hello raja:

Thank you very much!