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Jitter estimation on synchronous counter (Read 3982 times)
HdrChopper
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Jitter estimation on synchronous counter
Nov 09th, 2011, 4:54pm
 
Dear  colleagues,

Assuming I know how much jitter my reference clock has, I need to estimate de jitter of synchronous counter of N stages.
If the reference clock jitter is jck my gut feeling is that the total jitter should be jck*√N (assuming uncorrelated jitter between stages).

Is this correct? Any other considerations (or references)?

Thanks
Tosei
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Keep it simple
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rajkumar palwai
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Re: Jitter estimation on synchronous counter
Reply #1 - Nov 9th, 2011, 8:28pm
 
Tosei,
For any flip-flop, the inherent noise in the devices also add jitter at the o/p. So, if the ref clk has jitter of 'jck' and the device noise add a jitter of 'jdn', then the total jitter at the o/p would be rms average of jck & jdn.

For synchronous dividers, jitter doesn' accumulate between stages. Because the jitter at the o/p of the final flop just depends on the jck and its own noise at that time.
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rajkumar palwai
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Re: Jitter estimation on synchronous counter
Reply #2 - Nov 9th, 2011, 8:29pm
 
Jitter accumulation happens in ripple counters where, each stage jitter affects the next stage transition.
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