Old method of ECL latch.

Your latching mechanism feeds back a bias to shift the collectors of the input device.

Go digging in literature for ECL latch structures, probably in IEEE journals from 1970 era, or look into the Motorola 10,000 series ECL documents, from the same time period.

The circuit is part analog and part digital, so to speak.

You get the summation of two currents on the resistors. One current set is due to logic in and clock state, the other one is due to the current state of the data out.

When the logic in or clock is released the present state of the voltage is held on the resistors by the state of the data out signals at that point in time.

Set up a simple transient simulation and the functionality will be apparent.