I am designing PMOS CML Driver for 3.3Gbps and output swing is about 300mV with gnd-terminated 50ohm at TX and gnd-terminated 50ohm at RX.

The driver output swing can be small, but while designing pre-driver,
I found pre-driver output swing should be much higher than that of driver,
Of course, the Pre-driver is also PMOS CML buffer with gnd-terminated R.
And I found the output of pre-driver waveform had a lot of H/L skew because the fall-time is dependent on the R while rise-time is dependent on PMOS. But I can't decrease R because to get proper pre-driver swing decreasing R means pre-driver bias current should be increased.

So I am stuck at this problem.

Please let me know design technique of CML pre-driver if possible.

Thank U.

I attach my driver.
To get proper predriver output swing from 0 to about 700mV at Vdd 1.2V,
I use R1~400ohm , and Pre-driver output P/N cross point is about 400mV.

I want to know how pre-driver output waveform is and what is alternatives of big R or more current to get proper pre-driver swing,
and what is the proper pre-driver swing for this design.

Thank you for your attention.

Thanks loose-electron.

You suggested that the pre-driver should be CMOS inverter-type and it would be better to use clk boosting scheme. Am I right?
But, I heard "to make jitter and skew smaller, use identical buffer of even number" so, I made pre-driver CML.

Is it ok to use CMOS pre-driver of CML driver?
And if the output swing of Pre-driver is full swing,
then I think Data dependent jitter or H/L skew of Driver would be bigger.