I followed the paper, Modeling Jitter in PLL-based Frequency Synthesizers, wrote by Ken. I have a question after simulation. I try to verify how the system bandwidth affects the PLL output jitter when the VCO is the only noise source. So, I only put the accumulating jitter in VCO and all other blocks are ideal. I find that the output jitter almost doesn't change when I vary the system bandwidth of the PLL. This result doesn't make sense. The output jitter should decrease when I increase the system bandwidth of the PLL because the VCO noise see a high-pass filter. Do I do anything wrong? Does anyone get the same result?

Chris