Hello everyone,
       One of the input of CML buffer is a sine wave and the other input is biased by a appropriate DC. How the output of the buffer should be?
I supposed that the waveforms of the output terminals are differential all the same.
      But I found that the simulation result agrees with my thought only when the tail current source is an ideal current source (infinite output impedance). Why these happen? How the output impedance of the tail current source affect the outputs?

Thank you so much!

Yutao

Thanks for the explanation.
I did a experiment.
When the current source is implemented by a resistor, the phase shift between two output signals approaches 180 degree as the resistor increase.
When the current source is implemented by a current mirror, the phase shift between outputs is always 150 degree or so. Is it possible that the parasitic capacitor of the current mirror (Cgd, Cdb ) induces another pole?

Yutao Liu

Raj,
I am designing CML Buffer in 65nm,1.1V MOS and for Current source I am using current mirror with larger L(~500n) to avoid short channel effects.However, the input swing to the buffer is not exactly small(~300mVpp),so the tail node is not exactly at ac ground at all times,rather it follows the higher input after switching takes place and so the vds of the current source changes and hence the tail current.Any hint to solve the problem?