in most internal-chip RC osc, comparator is always used, sometimes two comp(one for VH threshold, one for VL threshold), and sometomes only one comp (the other threshold is ground maybe). however, the variation of VH or VL will influence the accuracy of osc output frequency,that is, generating different clock period Tclk for different cycles, so, clock jitter appears. then, how to minimize the influence of reference voltage variation(VH or VL) on clock frequency? what methods should be used normally if we have no off-chip large cap for reference voltage stabilization?

thanks.

Instead of plainly assuming the effect of VH and VL , i would suggest you run the simulation across few corners and then conclude.Also why dont you try the simple cap charged with current source tripping against reference for generating the clock?I had lots of problems tripping against 2 voltage references when i did this a few years ago.