in osc.jpg, it is the diagram of my osc, the voltage in CL(assuming node VI) is a ramp wave, but in simulation, i found that, the voltage of Vref1 and Vref2 is also changed with VI(ripple is about +/- 10mV), the amplitude is about 2% of VIpk-pk, i guess it is due to the capacitive coupling. and if i increase C1 and C2, or decrease the input pair size of comparator, the ripple in Vref1 and Vref2 decreases too. if i want to make Vref1 and Vref2 stable(ripple as small as possible), and not using very large C1 and C2(for area saving), not using very small input pair size for comparator(for good matching), is there any solution or method?thanks all for reply.

the comparator is non-compensated two-stage opamp plus inverter, and the input pair size is large(w*L=50u^2) for matching consideration. any advice or ideas?
besides, the power supply of osc is provided by a internally compensated LDO. thanks.

I would suggest using minimum possible length for input transistors,for 0.18u use 0.25u, it will reduce the parasitic capacitances and reduce coupling hence. One more point, although you maybe seeing a ripple, is it actually affecting output frequency accuracy. It could be that everytime during comparator comparison this may occur, but the comparator will have already compared against vref and this vref+delta might not actually affect you. Just run across corners and let us know.I believe you are using too large input transistors.You will need to reduce input sizes drastically from WL=50what is comparator bias current, less than 10u?Also please let us know what output accuracy you are trying to meet and the output frequency of the oscillator.