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The Designer's Guide Community Forum › Design › Analog Design › why gain drops a lot with increased sampling rate in PAC and PSTB simulations?
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why gain drops a lot with increased sampling rate in PAC and PSTB simulations? (Read 1881 times)
prcken
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why gain drops a lot with increased sampling rate in PAC and PSTB simulations?
Nov 09th, 2012, 2:49pm  
Hello,
I am so confused.
i am designing a fully differential opamp with precision gain of 2 used in pipeline ADC, when i replaced SC CMFB with ideal CMFB to do AC analysis in continuous time, i could get 66dB open loop gain of the opamp, then i put it in the switched-cap application, use pss+pstb to characterize the loop gain, it drops to about 20dB at 50MHz sampling rate.
i also tried and compared with PAC simulation for opamp open loop gain. it indeed shows gain drops as increasing sampling rate.
is that reliable to use PSTB and PAC to check the gain?
Looking forward to your reply.
Thanks!
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carlgrace
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Re: why gain drops a lot with increased sampling rate in PAC and PSTB simulations?
Reply #1 - Nov 9th, 2012, 2:57pm  
I don't know about PAC and PSTB analysis, but it sounds like to me like your common-mode loop isn't keeping up with the sampling rate.  If your common-mode loop is not able to stabilize your dc output voltage, then the output transistors of your OTA may not be biased in their high-gain regions.  They may be drifting too close to triode, which means their rout is dropping.  

This is my guess.  Check your common-mode level.
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prcken
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Re: why gain drops a lot with increased sampling rate in PAC and PSTB simulations?
Reply #2 - Nov 9th, 2012, 8:24pm  
hi, i double checked my CMFB, it works fine. i run transient to find when the key node voltages stable (e.g. CMFB) before PSS, because PSS need to fill in tstab (time for stabilization), CMFB fail could results in weird PAC or PSTB results/plot   
pss can also plot voltage vs. time, the time scale is one clock period, it shows all voltage levels are fine.
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