I have forced 500uA through the MOS as shown in figure 4. I kept Vds constant and varied Vgs from 0 to 1.1 v. And extracted Gm of MOS from the spice which is shown in fig 5.  
As per theory, when Vgs is far less from Vt i.e. means in WEAK INVERSION(WI) Gm is constant and depends only on the bias current (here it is 500uA).  Also Gm has to reduce from its maximum value when we move from  WEAK INVERSION (WI) to STRONG INVERSION (SI).

Question : Here in simulation that too in WI, why Gm starts increasing with Vgs first and later only in SI it starts falling?

Also in WI simulated values are not matching with theoretical values:
WI: Gm=(Id/nUt)=19.3mS. But in simulation Gm=400uS.
SI: at Vgs=0.6:  Gm=2Id/(Vgs-vt)=8mS but in simulation its around 1.4mS.
Theoretical values are kind of overestimating (Moreover velocity saturation effects are less at Vgs=0.6).  Is this the case with every one?


Regards,
Vinay Rao.

Thanks for your quick reply Raj. Here I attached the response: 1st row- ID through MOS, 2nd row- VDS, 3rd row: Gm.

Purpose:  I wanted to record the response of Gm w.r.t. Vgs when Id is constant. In simulation, I found 2 ways. First- keep constant current by varying W/L, second option to have constant current is to force ID by some ideal current source. Now I find second option is illogical to opt. But anyhow, how can I change W/L simultaneously with varying Vgs in simulation to record Gm vs Vgs in all 3 regions (WI, MI & SI)?

VDS: Here its coming around 6 volts. Though it's bit illogical-one question is striking me. Is that ideal current source which is charging Cdb and Cgd cap and increasing VDS to 6v?

Gm: Its true that in this case those equations becomes invalid. But if we observe in WI, we got large VDS value and still Gm is increasing w r t Vgs. How can I interpret this phenomenon?

Regards,
Vinay Rao

Hello Raj,
What you said is conceptually true but I am facing problem when I try to simulate your setup. Here is my spice code for your setup.

x1  d  g  0  0 NMOS  lf=0.06u wf=p nf=2 m=1 con=1 * MOS with W=p as a parameter
.param p=0.5u
Eopamp g 0 d ld MAX=1.1 MIN=0  1e6 *OPAMP with a gain of  1e6 and (g,0) as O/P and (d,ld) as I/P.
Vds  ld  0  DC  1.1 * Connecting  1.1 v to –ve terminal ld of OPAMP
Id d s DC 0.5m
Vdummy s 0 DC 1
.DC p 0.5u 8u 0.5u
.plot DC I(x1.mos) V(d) v(g)
.probe gm=par('gmo(x1.mos)')

When I am using opamp, both vd (drain voltage) and Id are becoming negative which is shown in figure (1st row-ID, 2nd row- Gm, 3rd row-Vg and 4th row- Vd.). Hence drain is becoming source and vice versa. Why Vd is becoming -ve in this setup instead of following opamp's other terminal voltage?  Vg (gate voltage) also would have gone into negative if I could have given negative minimum instead of zero to the opamp.

Gm: Gm is increasing w.r.t. W and this is what expected.

Id: At drain, we have one current from ideal current source and one more negative current flowing into the MOS. Is it not equally saying both the current are getting added at node DRAIN? If so then is it not violating KCL? Or am I misinterpreting the hspice expression I(x1.MOS) ? Where I am missing the string ?