The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 23rd, 2024, 7:39am
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Simulators › AMS Simulators › How to speed up simulation run time with VerilogA?
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
How to speed up simulation run time with VerilogA? (Read 3481 times)
Idan Kligvasser
New Member
*
Offline



Posts: 2
How to speed up simulation run time with VerilogA?
Dec 23rd, 2012, 8:11am  
Hi,

Is there is a way to speed up the simulation run time when using VerilogA blocks? Can i used compiled folders instead of compiling every time?

Thanks!
idan
Back to top
 
 
View Profile   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751
Re: How to speed up simulation run time with VerilogA?
Reply #1 - Dec 24th, 2012, 5:58pm  
Idan,

  Compiling is only performed when there have been changes to the
model, that is, when it is required.

                                                                          Sheldon
Back to top
 
 
View Profile   IP Logged
Idan Kligvasser
New Member
*
Offline



Posts: 2
Re: How to speed up simulation run time with VerilogA?
Reply #2 - Dec 27th, 2012, 4:56am  
thank you sheldon
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.