AS
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Posts: 18
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Raj,
I guess the answer is a bit tricky and depends on high-frequency PSRR i.e. compensation design. Generally speaking in PMOS driver designs dominant pole is located at the output, which is not the case in NMOS driver type designs. So, for a NMOS driver LDO the dominant pole at error amplifier remains somewhat fixed and the parasitic/secondary pole O/P at low currents move close-in. Thus, if you are coming from a PMOS LDO design, worst-case scenarios might get reversed.
-Aman
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