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base line wanderwall consideration (Read 7093 times)
raja.cedt
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base line wanderwall consideration
Feb 10th, 2013, 8:08am
 
Hello everyone,
can any one tell me how baseline wander spec specified in different standard? i guess it should be like how much droop in the signal when consecutive number of 1 or 0 given, so will they specify CID or droop rate? or low cuf-off frequency of the link?

One basic Question, since data entering into TX after coding (8B/10B or some other one) so there wont be any consecutive long 1's so how does it matter for a circuit ?

Thanks,
Raj.
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ywguo
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Re: base line wanderwall consideration
Reply #1 - Mar 2nd, 2013, 4:47am
 
Hi Raj.

For the 8B/10B code, the longest run of '1' or '0' is 4 bit. So don't worry about baseline wander.

Best Regards,
Yawei
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raja.cedt
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Re: base line wanderwall consideration
Reply #2 - Mar 2nd, 2013, 10:06am
 
Hello Yawei,
which standards are using 8B/10B and 64B/66B, i am in PCIE which standard, XAUI....like that ?

up to my knowledge 64B/66B has 64 long run of 0 or 1. So for this how they specify droop rate..Do you have good reference which explains coding considerations while designing driver?

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Raj.
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colossus_bade
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Re: base line wanderwall consideration
Reply #3 - Mar 22nd, 2013, 1:25am
 
The typical AC couple cap is 75~200nF in some specs(PCIE, USB3, SATA,...), and the high-pass corner formed by the AC-couple cap & termination resistor is relatively now, so I guess they wont specify the droop rate in the spec (it wont happen with this large ac-couple cap). But if you put your own ac couple capacitor in your silicon (typically much smaller than the spec value), you will worry about the droop of the signal, and the droop rate wont be specified in the spec (because it's caused by your specific design, not the spec)
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raja.cedt
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Re: base line wanderwall consideration
Reply #4 - Mar 22nd, 2013, 4:04am
 
hello colossus_bade,
Thanks for the reply, but i didn't understand why small AC coupling cap would require if there is already big cap on board, isn't it spoil the idea of having big cap on board??  can you explain little bit clear.
When you have you own cap inside will it have 50ohm or some higher imp???

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Raj.
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colossus_bade
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Re: base line wanderwall consideration
Reply #5 - Mar 24th, 2013, 7:49pm
 
Hi Raja,

Please check the pic below (from a JSSC paper), these on-chip ac couple caps are placed after the 50 ohm termination. I guess they are using those caps to isolate the 50ohm termination voltage & internal VGA input common mode voltage.
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input_ac_coup.png
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raja.cedt
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Re: base line wanderwall consideration
Reply #6 - Mar 25th, 2013, 7:54am
 
May i know paper title?

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Raj.
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colossus_bade
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Re: base line wanderwall consideration
Reply #7 - Mar 25th, 2013, 6:51pm
 
sure.

A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. JSSC 2011.12
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