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sigma delta modulator (Read 12898 times)
optimized
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sigma delta modulator
Feb 24th, 2013, 5:46pm
 
SA,
I am working on a PLL system design  and need a model for MASH 3rd order sigma delta modulator verilog A model
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sheldon
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Re: sigma delta modulator
Reply #1 - Mar 7th, 2013, 3:46pm
 
Optimized,

  I have built several system models for Delta Sigma modulators
using the Verilog A building blocks in the building blocks fro the
Noise Aware PLL flow library, pllMMLib(?) in Virtuoso. The blocks
were developed for simulating fractional-N PLLs. So while they
are not intended for your application, they will probably do okay.

                                                               Best Regards,

                                                                  Sheldon
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irisaru
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Re: sigma delta modulator
Reply #2 - Sep 13th, 2014, 9:04am
 
Hi Sheldon,

I am designing fractional-n pll using Cadence spectrerf, I designed Sigma delta modulator MASH 1-1-1 in transistor level but I do not know how to simulate its power spectral density.
Could you please give me some advices or give me some references for this simulation? I find in some paper that I need to do fft for output signal, however SDM Mash 1-1-1 has 3 bits output and I very concern about choosing what output to do fft.

Thank you so much,
Irisaru
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cheap_salary
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Re: sigma delta modulator
Reply #3 - Sep 13th, 2014, 10:13pm
 
irisaru wrote on Sep 13th, 2014, 9:04am:
I find in some paper that I need to do fft for output signal, however SDM Mash 1-1-1 has 3 bits output and I very concern about choosing what output to do fft.
Use ideal DAC made by Verilog-A to encode output bits to decimal number.

And you have to sample one deltaN per one clock period to apply FFT
This can be done by "sample" function of skill function in Cadence ADE.
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irisaru
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Re: sigma delta modulator
Reply #4 - Sep 14th, 2014, 7:59pm
 
Hi cheap_salary,

I would like to thank you for your help and support, this is my first project and I did not think about DAC because I have ever used verilog-A before.
I designed 3bit ideal DAC using modelwriter tools and connected it to SMD 111.
I saw in your pic that you used histogram to find the average value, could you please tell me how to do this? Does it similar to Monte-Carlo simulation?

I have another question: in my fractional-n pll, I use Multimodulus divider (MMD) created by 3 prescaler 2/3 cell. Then, I combine fractional divide signal and integer divide signal to control MMD. I read in some textbooks and papers that they use adder. However, does it require any special kind of adder? I used 3bit full adder to combine these signals, but the simulation has wrong divide.

Thank you,
Irisaru
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Re: sigma delta modulator
Reply #5 - Sep 14th, 2014, 11:45pm
 
irisaru wrote on Sep 14th, 2014, 7:59pm:
I saw in your pic that you used histogram to find the average value,
could you please tell me how to do this?
Does it similar to Monte-Carlo simulation?
Conventinal Transient Analysis over 65536*1usec which produce 65536 samples of deltaN.

irisaru wrote on Sep 14th, 2014, 7:59pm:
I have another question: in my fractional-n pll, I use Multimodulus divider (MMD) created by 3 prescaler 2/3 cell.
Then, I combine fractional divide signal and integer divide signal to control MMD.
I read in some textbooks and papers that they use adder.
However, does it require any special kind of adder?
I used 3bit full adder to combine these signals, but the simulation has wrong divide.
Ntotal=M*N+A, M=2 for your case.
So you have to control N and A.
When A is enough large, you may control only A,.
Otherwise, you have to control both N and A.
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Re: sigma delta modulator
Reply #6 - Sep 15th, 2014, 5:24am
 
Hi cheap_salary,

Thank you for your reply, I am sorry that I do not understand totally what you mean, I just joined IC design field few months ago.
I attached my simulation result in picture below. I use 20Mhz for clock and 4 bit accumulator for SDM, din<2:0> are SDM output and 3bit DAC input, dac_out is DAC output, I also use histo function in skill function to show histogram of DAC output. However it seems something went wrong because I set fractional is 3/16, but the result is not correct and I do not know how to show the mean and std like you do.
Could you please give me some advices or give me some references about this simulation?

Thank you so much,
Irisaru
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SDM_1.png
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Re: sigma delta modulator
Reply #7 - Sep 15th, 2014, 8:33am
 
irisaru wrote on Sep 15th, 2014, 5:24am:
I use 20Mhz for clock and 4 bit accumulator for SDM,
I can't believe bitwidth of accumulator is 4bits, it's too small.

irisaru wrote on Sep 15th, 2014, 5:24am:
din<2:0> are SDM output and 3bit DAC input, dac_out is DAC output,
I also use histo function in skill function to show histogram of DAC output.
However it seems something went wrong because I set fractional is 3/16, but the result is not correct
Simply you are wrong in decoding din<2:0> to decimal number using ideal DAC.
Your decoding output decimal codes are only positive.

Output codes as decimal number are {-3, -2, 1, 0, 1, 2, 3, 4} in MASH-111.
Usually these require 4 bits as output.
If you use 3 bits output, you have to invoke negative encode.

cheap_salary wrote on Sep 13th, 2014, 10:13pm:
And you have to sample one deltaN per one clock period to apply FFT
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Re: sigma delta modulator
Reply #8 - Sep 16th, 2014, 11:31pm
 
Hi cheap_salary,

cheap_salary wrote on Sep 15th, 2014, 8:33am:
I can't believe bitwidth of accumulator is 4bits, it's too small.

Thank you, I changed to 12bit accumulator for SDM.

cheap_salary wrote on Sep 15th, 2014, 8:33am:
Simply you are wrong in decoding din<2:0> to decimal number using ideal DAC. Your decoding output decimal codes are only positive.

I also modify ideal 3bit DAC (max voltage 4V, min voltage -3, threshold 1), however, it does not decode signed binary to decimal like MASH 111, it just changes 000 -> -3 and 111 -> 4. Therefore, I used (3bit full adder, 3bit full subtractor, 5 AND gate and 1 inverter) to change 3bit two's complement binary to 3bit simple binary, like (101 -> 000, 110 -> 001,..., 100 -> 111), and use the 3bit ideal DAC to decode to decimal number.
Do you think this is bad ideal ? I think it is complex and consume much power. Because the 3bit full adder and subtractor is not ideal, I think they will effect to SDM.
Do you think the problem in decoding to decimal is ideal 3bit DAC or I must use external components such as logic gates?

cheap_salary wrote on Sep 15th, 2014, 8:33am:
Output codes as decimal number are {-3, -2, 1, 0, 1, 2, 3, 4} in MASH-111.
Usually these require 4 bits as output.

Do you mean that mapping 3bit SDM output into 4bit binary before decode to decimal in ideal DAC?

Thanks,
Irisaru



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Re: sigma delta modulator
Reply #9 - Sep 21st, 2014, 10:42am
 
irisaru wrote on Sep 16th, 2014, 11:31pm:
I changed to 12bit accumulator for SDM.
Still small.
At least 16bits are required for MASH-111 to keep randomness.

irisaru wrote on Sep 16th, 2014, 11:31pm:
Do you mean that mapping 3bit SDM output into 4bit binary before decode to decimal in ideal DAC?
Show me mapping of din<2:0> to decimal number which you expect.

If 3bits are decoded as two's complementary code, it follows:
000 -> 0
001 -> 1
010 -> 2
011 -> 3
111 -> -1
110 -> -2
101 -> -3
111 -> -4

However, MASH-111 produces {-3, -2, 1, 0, 1, 2, 3, 4}.

Do you understand ?
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Re: sigma delta modulator
Reply #10 - Sep 22nd, 2014, 6:54pm
 
Hi cheap_salary,

Thank you very much. I think I understand what you mean.
I will modify idea DAC and accumulator.

Best regards,
Irisaru
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Re: sigma delta modulator
Reply #11 - Sep 22nd, 2014, 8:24pm
 
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