Hello everyone,

i'been experiencing some difference in spectre simulation results depending on which type of post pex netlist is created.

to track down the problem i've created a simple testbech.

My schematic is a capacitor with a switch transistor connected at the bottom plate. I've created a DRC and LVS clean layout.

I first do a PEX creating a calibreview output. Then i do a PEX creating only a spectre netlist output. Both PEX are same.

After a s-parameter simulation in order to check the capacitance seen at the  top plate I gete a 70 aF difference depending which netlist is used. (NMOS switch with grounded source and bulk is turned on).

Where could this difference come from? Please help me with some suggestions...  :)

Thanks in advance

Dear BOE,

thank you for your answer. Sorry for a late reply...i'll be faster from now on  :)

The netlists are different in terms of port node naming, but are the same when I compare the values of parasitic capacitors and resistors. Also, the device parameters and their values are the same.

nereo