john_ana
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Posts: 12
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Hi,
I am simulating a clock driven divider+25% duty generation circuit. Divider 's output is 50% duty with I/Q phases. These clocks went through inverters and NAND gates to get 25% duty.
I tried couple of PSS+PNOISE methods, such as the one using PNOISE with noise type=source, noise type=jitter and noise type=timedomain.
From all simulation results, it seems the buffered I/Q has the worst phase noise/jitter ,while the NANDed output get better phase noise/jitter.
As shown in the attached noise type=source PNOISE sim result, node out1 is divider output, node x2 is one buffer after, node I/Q are after multiple buffers, node I25 is after the "NAND" gate.
I tried noise type=jitter with a 0.5 threshold, and find the integrated (100K to 200M) Jee@ out1=6.7f, Jee@I is about 24f, and Jee@I25 is only 4f.
It seems phase noise/jitter get improved in the chain of buffer/nand gates? For a simple chain of inverters, I think phase noise/jitter degradations are accumulative, i.e. the jitters at different stages are uncorrelated and the jitter caused in one stage can not be corrected or compensated by later stages. How to explain the improved jitter/phase noise?
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