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Does the intrinsic gate resistance of a mos introduce noise? (Read 4375 times)
dog1
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Does the intrinsic gate resistance of a mos introduce noise?
Mar 12th, 2014, 7:32am
 
I am designing an LNA and find that the intrinsic gate resistance of a mos in the IIR model seems to be handy when doing input matching. However, I want to know if it will introduce noise. If its noise performance is like a passive resistor, then there is no good reason to use it in the input matching.

Thanks!
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BackerShu
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Re: Does the intrinsic gate resistance of a mos introduce noise?
Reply #1 - Dec 16th, 2014, 2:17pm
 

I am not sure what do you mean by IIR model here. But the gate resistance does influence the noise performance, especially like the case in LNA design. That's why multiple finger device is usually used, and even double side gate connection is recommended to optimized noise if necessary.

Of course, this comes with the trade-off between bandwidth and noise.
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raja.cedt
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Re: Does the intrinsic gate resistance of a mos introduce noise?
Reply #2 - Dec 17th, 2014, 9:23am
 
Hi,
I don't think there is trade off between noise and bandwidth, extra capacitance due to multiple gate connections could easily tuned out by gate inductor provided this LNA is going to be used in typical narrow band RF amp.

Once gate fingers reach certain number I think gate resistance will increase because intrinsic poly res will decrease but extra routing resistance will increase..i am not sure about this point, just guessing

Thanks,
Raj.

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Dshoter
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Re: Does the intrinsic gate resistance of a mos introduce noise?
Reply #3 - Apr 18th, 2015, 6:11am
 
raja.cedt wrote on Dec 17th, 2014, 9:23am:
Hi,
I don't think there is trade off between noise and bandwidth, extra capacitance due to multiple gate connections could easily tuned out by gate inductor provided this LNA is going to be used in typical narrow band RF amp.

Once gate fingers reach certain number I think gate resistance will increase because intrinsic poly res will decrease but extra routing resistance will increase..i am not sure about this point, just guessing

Thanks,
Raj.


What you are saying about the resistance increasing after a certain number of fingers (and width ratio) is true. You should check on the process documentation to check for these details.
Usually they provide the maximum number of fingers, and width per finger until this phenomenon occurs. This and other stuff, like capacitance variations with fingers and width usually are described in the process documentation.

With best regards.
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