hi, all
 in tsmc 40nm pdk model, I find its stress requirement. it is attached below.
 my question is why "vbs" is limited to +/- 1.2*Vdd.
 vbs is a pn junction , so it can hold high reverse biased voltage, right???

The picture you posted looks to talk about model validity, not stress limits. Generally, foundries don't want to guarantee model accuracy over ranges where they have not measured.