Hi all,

I am new to here, and I am doing some analog and mix-mode design now.

I try to save digital signals ( all the digital signal in the design, not just the output of digital part) in the verilog code as follows:
 initial
 begin
  $dumpfile( "wave.vcd");
  $dumpvars( 0, digital);
 end

But I found the saved waveform only have initial value, all that after initialization don't exist.

The analog part works well, and the output of the digital part is right send to analog part. Thus, I guess the fault located in the saving.

How do you save the digital signals using verilog?
How to fix this problem?

Thank your for your patience~

Wendy

Since your saving is done in an "initial" block, why are you surprised that you only get initial values?

This can be tool specific. Tell us more about your situation.

-Ken